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undergraduate thesis
Dizajn jednostavnog procesora arhitekture RISC-V za programabilnu logiku
2020. urn:nbn:hr:168:929873
Vučić, Mirela
University of Zagreb
Faculty of Electrical Engineering and Computing

Cite this document

Vučić, M. (2020). Dizajn jednostavnog procesora arhitekture RISC-V za programabilnu logiku (Undergraduate thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:929873

Vučić, Mirela. "Dizajn jednostavnog procesora arhitekture RISC-V za programabilnu logiku." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2020. https://urn.nsk.hr/urn:nbn:hr:168:929873

Vučić, Mirela. "Dizajn jednostavnog procesora arhitekture RISC-V za programabilnu logiku." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2020. https://urn.nsk.hr/urn:nbn:hr:168:929873

Vučić, M. (2020). 'Dizajn jednostavnog procesora arhitekture RISC-V za programabilnu logiku', Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 12 April 2024, https://urn.nsk.hr/urn:nbn:hr:168:929873

Vučić M. Dizajn jednostavnog procesora arhitekture RISC-V za programabilnu logiku [Undergraduate thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2020 [cited 2024 April 12] Available at: https://urn.nsk.hr/urn:nbn:hr:168:929873

M. Vučić, "Dizajn jednostavnog procesora arhitekture RISC-V za programabilnu logiku", Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2020. Available at: https://urn.nsk.hr/urn:nbn:hr:168:929873

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Metadata
TitleDizajn jednostavnog procesora arhitekture RISC-V za programabilnu logiku
Title (english)Simple RISC-V Processor Design for Programmable Logic
AuthorMirela Vučić
MentorJosip Knezović (mentor)
Committee memberJosip Knezović (predsjednik povjerenstva)
Committee memberBranimir Pervan (član povjerenstva)
Committee memberEmanuel Guberović (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2020-09-15, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Abstract
U ovom radu opisan je osnovni skup instrukcija arhitekture RISC-V. Detaljno je opisan osnovni cjelobrojni 32-bitni skup naredbi RV32I te standardna proširenja zamrznutog dizajna. Prikazane su mogućnosti i konvencije programiranja u zbirnom jeziku. Dizajn jednostavnog puta podataka i kontrolne jedinice za RISC-V procesor predstavljen je na primjeru Ibex jezgre. Opisani su osnovni koraci definiranja i dodavanja nove instrukcije u skup naredbi RISC-V. Također je opisan i postupak dodavanja nove naredbe u postojeću jezgru te postupak simulacije u svrhu validacije instrukcije.
Abstract (english)
This bachelor thesis describes the RISC-V instruction set architecture and the standard extensions of the base set. The base 32-bit integer instructions set RV32I is described in detail, along with the frozen extensions. Assembly language programming possibilities and conventions are shown in this work. The design of a simple datapath and control unit for a RISC-V processor is presented on the example of an Ibex core. Basic steps required for defining and adding a new instruction to the RISC-V instruction set are described. The process of adding a new instruction to the existing core and also the process of simulating the instruction for validation are described.
Keywords
Keywords (english)
Languageenglish
URN:NBNurn:nbn:hr:168:929873
Study programmeTitle: Computing
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
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Created on2023-01-13 16:29:53