RISC-V jezgra s Axi4-lite memorijom spojenom putem mreže na čipu

master's thesis

• Title (english): RISC-V core with Axi4-lite memory connected via a network on chip
• Author: Tomislav Katanić
• Mentor: Daniel Hofman (mentor)
• Committee member: Daniel Hofman (predsjednik povjerenstva)
• Committee member: Danko Basch (član povjerenstva)
• Committee member: Josip Knezović (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2022-02-22, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing

Abstract

U ovome radu je prikazana i objašnjena implementacija RV32I arhitekture skupa instrukcija koja predstavlja osnovni skup instrukcija RISC-V arhitekture za rad s cijelim brojevima. Korišteni RV32I procesor je prilagođen za rad s BRAM-om i mrežom na čipu. Ostvaren je sustav na čipu koji se sastoji od RV32I procesora, BRAM-a i mreže na čipu. Razvijena je komponenta AXI4-Lite Adapter koja služi za spajanje procesora s ostalim AXI4-Lite IP komponentama. Procesor je spojen pomoću AXI4-Lite Adaptera na AXI4-Lite Master sučelje mreže na čipu, a BRAM je spojen na AXI4-Liste Slave sučelje mreže na čipu. Napravljena je analiza performansi, opisano je ponašanje procesora i sustava na čipu te je predložen daljnji razvoj.

Abstract (english)

This paper presents and explains the implementation of the RV32I instruction set architecture, which is the basic instruction set of the RISC-V architecture for working with integers. The RV32I processor used in this paper is adapted to work with BRAM and network on chip. A system on chip consisting of an RV32I processor, BRAM and a network on chip is implemented. The AXI4-Lite Adapter component has been developed to connect the processor to other AXI4-Lite IP cores. The processor is connected using the AXI4-Lite Adapter to the AXI4-Lite Master interface of the network on chip, and the BRAM is connected to the AXI4-Lite Slave interface of the network on chip. Performance analysis was performed, the behavior of processor and system on chip was described, and further development was proposed.

• Keywords: procesor; RISC-V; RV32I; implementacija procesora; procesorska jezgra; arhitektura skupa instrukcija; memorija; pristup memoriji; AXI4-Lite sučelje; mreža na čipu; usmjeritelj; instrukcije; sustav na čipu; AXI master; AXI slave
• Keywords (english): processor; RISC-V; RV32I; CPU core implementation; CPU core; instruction set architecture; memory; memory access; AXI4-Lite interface; network on chip; router; instructions; system on chip; AXI master; AXI slave
• Language: croatian
• URN:NBN: urn:nbn:hr:168:181638
• Study programme: Title: Computing; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2023-01-13 15:16:06