University of Zagreb Faculty of Electrical Engineering and Computing
Cite this document
Katanić, T. (2022). RISC-V jezgra s Axi4-lite memorijom spojenom putem mreže na čipu (Master's thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:181638
Katanić, Tomislav. "RISC-V jezgra s Axi4-lite memorijom spojenom putem mreže na čipu." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2022. https://urn.nsk.hr/urn:nbn:hr:168:181638
Katanić, Tomislav. "RISC-V jezgra s Axi4-lite memorijom spojenom putem mreže na čipu." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2022. https://urn.nsk.hr/urn:nbn:hr:168:181638
Katanić, T. (2022). 'RISC-V jezgra s Axi4-lite memorijom spojenom putem mreže na čipu', Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 09 December 2024, https://urn.nsk.hr/urn:nbn:hr:168:181638
Katanić T. RISC-V jezgra s Axi4-lite memorijom spojenom putem mreže na čipu [Master's thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2022 [cited 2024 December 09] Available at: https://urn.nsk.hr/urn:nbn:hr:168:181638
T. Katanić, "RISC-V jezgra s Axi4-lite memorijom spojenom putem mreže na čipu", Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2022. Available at: https://urn.nsk.hr/urn:nbn:hr:168:181638