University of Zagreb Faculty of Electrical Engineering and Computing
Cite this document
Furlan, J. (2020). Dizajn sustava za prepoznavanje gesti temeljenog na FPGA sklopu i procesorskoj jezgri (Undergraduate thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:223272
Furlan, Jan. "Dizajn sustava za prepoznavanje gesti temeljenog na FPGA sklopu i procesorskoj jezgri." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2020. https://urn.nsk.hr/urn:nbn:hr:168:223272
Furlan, Jan. "Dizajn sustava za prepoznavanje gesti temeljenog na FPGA sklopu i procesorskoj jezgri." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2020. https://urn.nsk.hr/urn:nbn:hr:168:223272
Furlan, J. (2020). 'Dizajn sustava za prepoznavanje gesti temeljenog na FPGA sklopu i procesorskoj jezgri', Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 30 November 2024, https://urn.nsk.hr/urn:nbn:hr:168:223272
Furlan J. Dizajn sustava za prepoznavanje gesti temeljenog na FPGA sklopu i procesorskoj jezgri [Undergraduate thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2020 [cited 2024 November 30] Available at: https://urn.nsk.hr/urn:nbn:hr:168:223272
J. Furlan, "Dizajn sustava za prepoznavanje gesti temeljenog na FPGA sklopu i procesorskoj jezgri", Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2020. Available at: https://urn.nsk.hr/urn:nbn:hr:168:223272