Procesor arhitekture RISC-V prilagođen za implementaciju u programabilnoj logici

undergraduate thesis

• Title (english): RISC-V Processor Customized for Programmable Logic Implementation
• Author: Mihael Kovač
• Mentor: Josip Knezović (mentor)
• Committee member: Josip Knezović (predsjednik povjerenstva)
• Committee member: Daniel Hofman (član povjerenstva)
• Committee member: Branimir Pervan (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2019-07-12, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing

Abstract

Zbog svoje modularnosti, RISC-V, bez licenca i bez naknada skup instrukcija, može služiti za dizajniranje i implementaciju bilo kakvih računalnih sustava, od mikročipova do superračunala. To je stabilan skup instrukcija koji je dizajniran za specijalizaciju i ekstenzibilnost. Zbog toga, simulacija RISC-V jezgre, memorije i okruženja izvršenja, može nam služiti za testiranje isplativosti raznih korisničkih modula prije same implementacije.
Dok nam simulacija korištenjem programskog jezika kao što je C++, može prikazati način rada jezgre, implementacija u programibilnoj logici na FPGA ploćici može nam približiti samu hardversku implementaciju.

Abstract (english)

Because of it's modularity, the licence-free, royalty-free RISC-V instruction set arhitecture,
can be used in the design and implementation of any computer system from microchips to supercomputers. It is a stable ISA which is designed for extensibility and specialization. Therefore, a simulation of a RISC-V core, memory and an execution environment in which the core executes instructions can be used to test the profitability of custom, user-made modules before their actual implementation. While the a C++ simulation of a RISC-V core can give us insight into the workings of an actual core, the implementation in programmable logic for a FPGA board can bring us closer to the actual hardware implementation.

• Keywords: RISC-V; ISA; Memorija; Register; C++; Simulacija; FPGA; Instrukcija; Procesor; Arhitektura; Jezgra
• Keywords (english): RISC-V; ISA; Memory; Register; C++; Processor; Arhitecture; Core; FPGA; Instruction
• Language: english
• URN:NBN: urn:nbn:hr:168:627464
• Study programme: Title: Computing; Study programme type: university; Study level: undergraduate; Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2020-01-07 19:17:11