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master's thesis
Synthesizer of Simplified VHDL-Based Model for GAL16v8

Deni Munjas (2017)
University of Zagreb
Faculty of Electrical Engineering and Computing
Cite this document...

Munjas, D. (2017). Izgradnja sintetizatora pojednostavljenog VHDL-modela za GAL16v8 (Master's thesis). Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:228798

Munjas, Deni. "Izgradnja sintetizatora pojednostavljenog VHDL-modela za GAL16v8." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2017. https://urn.nsk.hr/urn:nbn:hr:168:228798

Munjas, Deni. "Izgradnja sintetizatora pojednostavljenog VHDL-modela za GAL16v8." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2017. https://urn.nsk.hr/urn:nbn:hr:168:228798

Munjas, D. (2017). 'Izgradnja sintetizatora pojednostavljenog VHDL-modela za GAL16v8', Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 26 May 2019, https://urn.nsk.hr/urn:nbn:hr:168:228798

Munjas D. Izgradnja sintetizatora pojednostavljenog VHDL-modela za GAL16v8 [Master's thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2017 [cited 2019 May 26] Available at: https://urn.nsk.hr/urn:nbn:hr:168:228798

D. Munjas, "Izgradnja sintetizatora pojednostavljenog VHDL-modela za GAL16v8", Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2017. Available at: https://urn.nsk.hr/urn:nbn:hr:168:228798