Senzor za mjerenje vođenih smetnji na čipu

master's thesis

• Title (english): On-chip conducted emissions sensor
• Author: Luka Sabljak
• Mentor: Adrijan Barić (mentor)
• Committee member: Adrijan Barić (predsjednik povjerenstva)
• Committee member: Marko Koričić (član povjerenstva)
• Committee member: Tvrtko Mandić (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2022-07-15, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Electrical Engineering

Abstract

U ovome radu objašnjen je postupak projektiranja senzora za mjerenje vođenih smetnji na čipu u 180 nm CMOS tehnologiji. Rad se sastoji od dviju cjelina. U prvoj se teorijski objašnjavaju dijelovi sklopa: uvodsko sljedilo, komparator, SR bistabil i jedinica za obradu podataka, a u drugom su prikazani rezultati simulacija u programskom alatu za simulaciju sustava Cadence Virtuoso. Napravljene su istosmjerne i izmjenične analize, Monte Carlo simulacijama određeno je vrijeme kašnjenja i napon pomaka sklopa i naposljetku simulirana je pogreška senzora koja sadržava sve prethodne karakteristike sklopa. Crtanjem topološkog nacrta, ekstrakcijom parazitnih elemenata i simulacijom sklopa s parazitnim elementima utvrđeno je konačno ponašanje sklopa.

Abstract (english)

The process of designing the on-chip conducted emissions sensor in 180 nm CMOS technology is explained in this paper. The paper is split into two parts. In the first part, the function of each part of the circuit: source follower, comparator, SR latch and data processing unit is explained, and in the second the results of the simulations, which were run by the Cadence Virtuoso simulation system software, are shown. There were DC and AC analyses made, delay time and offset voltage were determined by Monte Carlo simulations, and, lastly, the error of the sensor was simulated, which contains all previously mentioned characteristics. The behavior of the final circuit is determined by drawing of the layout, extraction of parasitic elements and post-layout simulation.

• Keywords: mikroelektronika; dizajn čipa; CMOS tehnologija; senzor; komparator; Verilog-A
• Keywords (english): microelectronics; chip design; CMOS tehnology; sensor; comparator; Verilog-A
• Language: croatian
• URN:NBN: urn:nbn:hr:168:392353
• Study programme: Title: Electrical Engineering and Information Technology; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije (magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2023-01-14 09:53:05