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undergraduate thesis
Simulacijski model računalnog sustava s procesorom arhitekture RISC-V za programski paket SSPARCS
2021. urn:nbn:hr:168:756195
Lehpamer, Lovro
University of Zagreb
Faculty of Electrical Engineering and Computing

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Lehpamer, L. (2021). Simulacijski model računalnog sustava s procesorom arhitekture RISC-V za programski paket SSPARCS (Undergraduate thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:756195

Lehpamer, Lovro. "Simulacijski model računalnog sustava s procesorom arhitekture RISC-V za programski paket SSPARCS." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2021. https://urn.nsk.hr/urn:nbn:hr:168:756195

Lehpamer, Lovro. "Simulacijski model računalnog sustava s procesorom arhitekture RISC-V za programski paket SSPARCS." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2021. https://urn.nsk.hr/urn:nbn:hr:168:756195

Lehpamer, L. (2021). 'Simulacijski model računalnog sustava s procesorom arhitekture RISC-V za programski paket SSPARCS', Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 12 April 2024, https://urn.nsk.hr/urn:nbn:hr:168:756195

Lehpamer L. Simulacijski model računalnog sustava s procesorom arhitekture RISC-V za programski paket SSPARCS [Undergraduate thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2021 [cited 2024 April 12] Available at: https://urn.nsk.hr/urn:nbn:hr:168:756195

L. Lehpamer, "Simulacijski model računalnog sustava s procesorom arhitekture RISC-V za programski paket SSPARCS", Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2021. Available at: https://urn.nsk.hr/urn:nbn:hr:168:756195

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Metadata
TitleSimulacijski model računalnog sustava s procesorom arhitekture RISC-V za programski paket SSPARCS
Title (english)RISC-V System Simulation Model for SSPARCS Simulation Platform
AuthorLovro Lehpamer
MentorJosip Knezović (mentor)
Committee memberJosip Knezović (predsjednik povjerenstva)
Committee memberBranimir Pervan (član povjerenstva)
Committee memberLuka Macan (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2021-09-14, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Abstract
RISC-V nova je arhitektura procesora koja bi zahvaljujući svojoj modularnosti i otvorenosti mogla naći široku primjenu, kako u obrazovanju, tako i u industriji. Ovaj je rad razmatrao primjenu arhitekure u kontekstu obrazovanja proučavajući simulaciju računalnog sustava temeljenog na zamišljenom RISC-V procesoru. Krajnji proizvod je ostvaren korištenjem programskog paketa SSPARCSS i programskog jezika C, a korisnicima omogućuje izvođenje programa pisanih u RISC-V mnemoničkom jeziku na simuliranom procesoru, kao i rad sa simuliranim ulaznim i izlaznim jedinicama.
Abstract (english)
RISC-V is a new processor architecture that could, thanks to its modularity and openness, find widespread use in both education and industry applications. This thesis looked at the usefulness of the architecture in an educational context by studying the simulation of a computer system based on an imaginary RISC-V processor. The end product was realized using the SSPARCSS software and the C programming language, and it allows the user to execute programs written in the RISC-V assembly language on the simulated processor as well as to use the simulated input and output units.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:756195
Study programmeTitle: Computing
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
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Created on2023-01-14 09:15:56