Implementacija 32-bitne RISC-V instrukcijske arhitekture otvorenog koda u FPGA sklopovlju

master's thesis

• Title (english): Implement a 32-bit RISC-V open-source instruction architecture in an FPGA hardware
• Author: Ivan Žuglić
• Mentor: Daniel Hofman (mentor)
• Committee member: Daniel Hofman (predsjednik povjerenstva)
• Committee member: Danko Basch (član povjerenstva)
• Committee member: Josip Knezović (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2021-06-29, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing

Abstract

U ovome radu je prikazana i objašnjena cjelokupna implementacija RISC-V arhitekture osnovnog skupa instrukcija (RV32I). Dano je objašnjenje formata implementiranih instrukcija i pojedinih komponenti arhitekture koje su potrebne za njihovo ispravno izvođenje, te je naveden cjelokupni programski kod implementacije opisane arhitekture, kao i kodovi ispitnih programa kojima se provjerava ispravnost izvođenja pojedinih instrukcija u simulaciji i na ZedBoard FPGA sklopovlju. Također je napravljena analiza performansi i predložen je daljnji razvoj arhitekture.

Abstract (english)

This thesis describes and explains the entire implementation of RISC-V base instruction set architecture (RV32I). An explanation on the format of the implemented instructions is given, along with the explanation of each individual component of the architecture which is needed for their proper execution. In addition, the entire programming code of the architecture is given and explained as well as programming code of the test programs which check validity of the executed instructions in both the simulation and the ZedBoard FPGA. Performance analysis is also given, along with the proposal of the future development.

• Keywords: RISC-V; RV32I; arhitektura skupa instrukcija; format instrukcije; implementacija arhitekture skupa instrukcija; implementacija procesorske jezgre
• Keywords (english): RISC-V; RV32I; instruction set architecture; instruction format; instruction set architecture implementation; CPU core implementation
• Language: croatian
• URN:NBN: urn:nbn:hr:168:561059
• Study programme: Title: Computing; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2023-01-13 16:33:03