Implementacija procesorske jezgre Arm Cortex-M23 na FPGA platformi

master's thesis

• Title (english): Implementation of Arm Cortex-M23 processor core on FPGA platform
• Author: Tin Sorić
• Mentor: Adrijan Barić (mentor)
• Committee member: Adrijan Barić (predsjednik povjerenstva)
• Committee member: Jurica Kundrata (član povjerenstva)
• Committee member: Vladimir Čeperić (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2022-07-08, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Electrical Engineering

Abstract

U ovom radu ukratko je opisana ARM Cortex-M23 procesorska jezgra, kao i njene
funkcionalnosti. Naglasak rada bio je na implementaciji procesorske jezgre na ra-
zvojnom sustavu temeljenom na Xilinx FPGA čipu. Korištenjem verilog koda koji je
dostupan od strane ARM korporacije, bilo je potrebno preoblikovati i prilagoditi dizajn
implementaciji za ciljani FPGA sklop. Uvidom u arhitekturu jezgre i razumijevanjem
verilog koda moguće je izmijeniti dizajn procesora, ovisno o željenim parametrima
kao što su zauzeće resursa na FPGA, frekvencija takta, potrošnja, kapacitet memorija,
periferno sklopovlje i slično. Nakon detaljnog opisa sabirničke arhitekture i memorija,
prikazane su simulacije kojima se verificira ispravan dizajn, nakon čega slijedi im-
plementacija i analiza pojedinih parametara. Kao verifikacija ispravnog rada dizajna
implementiran je testni C kod koji je tijekom implementacije ugrad̄en u programsku me-
moriju, te upravlja GPIO priključcima, kako bi iz vana mogli provjeriti ispravnost.

Abstract (english)

This paper briefly describes the ARM Cortex-M23 processor core, as well as its functionalities. The emphasis of the work was on the implementation of the processor core on a development system based on the Xilinx FPGA chip. Using verilog code available from ARM Corporation, the code needed to be redesigned and adapted for implementation for the target FPGA device. By understanding the core architecture and understanding the verilog code, it is possible to change the design of the processor, depending on the desired parameters such as resource utilization on the FPGA, clock frequency, power consumption, memory capacity, peripherals and so on. After a detailed description of the bus architecture and memory, simulations are presented to verify the correct design, followed by the implementation and analysis of individual parameters. As a verification of the correct operation of the design, a test C code was implemented, which was built into the program memory during implementation, and manages GPIO connections, so that they could be verified from the outside.

• Keywords: FPGA; Verilog; Digitalni dizajn; ARM; Procesorska jezgra; Sabirnica; RAM/ROM memorija
• Keywords (english): FPGA; Verilog; Digital design; ARM; Processor core; Bus architecture; RAM/ROM memory
• Language: croatian
• URN:NBN: urn:nbn:hr:168:606568
• Study programme: Title: Electrical Engineering and Information Technology; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije (magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2023-01-13 16:06:46