Funkcionalna verifikacija SPI protokola

master's thesis

• Title (english): Functional Verification of the SPI Protocol
• Author: Lovro Levak
• Mentor: Dražen Jurišić (mentor)
• Committee member: Dražen Jurišić (predsjednik povjerenstva)
• Committee member: Mladen Vučić (član povjerenstva)
• Committee member: Goran Molnar (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2021-06-30, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Electrical Engineering

Abstract

U ovom radu razvijena je UVM Verifikacijska komponenta (engl. UVM Verification Component) s ciljem funkionalne verifikacije SPI protokola. Temeljena je na Univerzalnoj Verifikacijskoj Metodologiji (engl. Universal Verification Methodology), koja je de-facto standard u verifikaciji digitalne logike današnjice, pri čemu se koristi pristup slučajno generirane pobude, te egzaktnog praćenja rezultata verifikacije. S ciljem ubrzanja razvoja verifikacijske komponente, korišten je UVMF (engl. UVM Framework). UVMF sadrži klase koje nasljeđuju UVM bazne klase, skripte za generiranje koda, dokumentaciju i primjere. Skripte za opis UVM komponenti napisane se u YAML-u (engl. YAML Ain't Markup Language). YAML omogućuje visoku razinu apstrakcije, pa je dobra metoda za povezivanje UVM komponenti. Verifikacijski plan bio je uspoređivati ulaze s izlazima iz komponete. Ako su oni jednaki, funkcionalnost SPI protokola bila bi potvrđena. UVC podržava sve SPI načine rada, kao i skup parametara poput duljine okvira podataka i broja transakcija. Razvijena komponenta sadrži i upravljač i izvršilac. Naposlijetku, testovi su napisani za korištenje komponente.

Abstract (english)

In this project, a Universal Verification Component (UVC) was developed in order to functionally verify SPI protocol. It is based on Universal Verification Methodology (UVM), which is a de-facto standard in constrained-random metric-driven verification of digital logic in the industry today. To speed up the process of developing the UVC, UVM Framework was used. It contains a class library that extends UVM base class library, and provides scripts for code generation, documentation and examples. Script inputs, such as UVM component details, were written in YAML (YAML Ain't Markup Language). YAML provides high-level of abstraction inputs, and thus is less error prone method of connecting the UVM components. Verification plan was to compare inputs and outputs of the DUT, and if they matched, SPI functionality would be verified. UVC was made to be able to support all SPI modes, as well as multiple parameters, such as frame length and number of transactions. The developed UVC contains both SPI primary and secondary. Finally, tests were written to run the UVC.

• Keywords: UVM; UVMF; SPI; Funkcionalna Verifikacija
• Keywords (english): UVM; UVMF; SPI; Functional Verification
• Language: english
• URN:NBN: urn:nbn:hr:168:607636
• Study programme: Title: Electrical Engineering and Information Technology; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije (magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2023-01-13 12:53:04