Integracija akceleratora za duboko učenje u heterogeni računalni sustav zasnovan na procesoru arhitekture RISC-V

master's thesis

• Title (english): Deep Learning Accelerator Integration in Heterogeneous Computing RISC-V System
• Author: Mihael Kovač
• Mentor: Josip Knezović (mentor)
• Committee member: Josip Knezović (predsjednik povjerenstva)
• Committee member: Hrvoje Mlinarić (član povjerenstva)
• Committee member: Daniel Hofman (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2021-07-15, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing

Abstract

Rastom popularnosti i složenosti dubokih neuronskih mreža, potreba za uređajima visokih
performansi sve je veća. Specifično težak problem postaje izvođenje takvih, složenih modela na
uređajima vrlo niske razine snage, što je slučaj u sve popularnijim sustavima Interneta Stvari (IoT).
Cilj ovog rada je integrirati NVIDIA-in sklopovski akcelerator za neuronske mreže u sustav sklopovski sustav niske snage, baziran na arhitekturi procesora RISC-V. Taj sklopovski sustav pruža PULP platforma, platforma otvorenog koda za istraživanje i razvoj ugradbenih računala.
Prilagođen je NVIDIA-in akcelerator za integraciju u PULP-ov sustav PULPissimo. Opisani
su koraci integracije i testiranja cijelog sustava. Uspoređeno je s drugim sličnim, suvremenim implementacijama.

Abstract (english)

As the popularity and complexity of deep neural networks grows, the need for high performance
devices is increasing. Using such complex, deep models can be particularly difficult on ultra-low power devices, which is the case in the rising field of Internet of Things (IoT) systems.
The goal of this thesis is to integrate NVIDIA's deep learning hardware accelerator into an ultra-low power hardware system, based on a RISC-V processor architecture. This hardware system is provided by the PULP platform, an open-source platform for research and development of embedded systems. NVIDIA's deep learning accelerator is first adapted, then integrated into a PULP System-on-Chip (SoC), PULPissimo. The integration and testing steps are described and the result is compared to other state-of-the-art implementations with similar use-cases.

• Keywords: PULP; NVDLA; NVIDIA; Duboko Učenje; Umjetna Inteligencija; Sklopovski Akceleratori; Verilator; Dizajn Sklopovlja; Integracija na razini sustava
• Keywords (english): PULP; NVDLA; NVIDIA; Deep Learning; AI; Hardware Accelerators; Verilator; Hardware Design; System-On-Chip
• Language: english
• URN:NBN: urn:nbn:hr:168:887429
• Study programme: Title: Computing; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2023-01-13 12:44:42