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undergraduate thesis
Simulacija obrade videa na procesoru RISC-V s gem5 simulatorom
2020. urn:nbn:hr:168:358247
Konić, Filip
University of Zagreb
Faculty of Electrical Engineering and Computing

Cite this document

Konić, F. (2020). Simulacija obrade videa na procesoru RISC-V s gem5 simulatorom (Undergraduate thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:358247

Konić, Filip. "Simulacija obrade videa na procesoru RISC-V s gem5 simulatorom." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2020. https://urn.nsk.hr/urn:nbn:hr:168:358247

Konić, Filip. "Simulacija obrade videa na procesoru RISC-V s gem5 simulatorom." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2020. https://urn.nsk.hr/urn:nbn:hr:168:358247

Konić, F. (2020). 'Simulacija obrade videa na procesoru RISC-V s gem5 simulatorom', Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 14 November 2024, https://urn.nsk.hr/urn:nbn:hr:168:358247

Konić F. Simulacija obrade videa na procesoru RISC-V s gem5 simulatorom [Undergraduate thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2020 [cited 2024 November 14] Available at: https://urn.nsk.hr/urn:nbn:hr:168:358247

F. Konić, "Simulacija obrade videa na procesoru RISC-V s gem5 simulatorom", Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2020. Available at: https://urn.nsk.hr/urn:nbn:hr:168:358247

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Metadata
TitleSimulacija obrade videa na procesoru RISC-V s gem5 simulatorom
Title (english)Simulation of video processing on an RISC-V processor with a gem5 simulator
AuthorFilip Konić
MentorDaniel Hofman (mentor)
Committee memberDaniel Hofman (predsjednik povjerenstva)
Committee memberAlen Duspara (član povjerenstva)
Committee memberLuka Macan (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2020-07-07, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Abstract
Simulacijom procesora i računalnih sustava omogućava se istraživanje u području arhitekture i organizacije računala. Dostupno je nekoliko takvih platformi koje omogućuju simulaciju, emulaciju i sintezu proizvoljnih arhitektura skupa instrukcija. Predstavlja se građa gem5 simulatora, opisuju specifičnosti RISC-V skupa instrukcija te implementacija RISC-V ISA u gem5 simulatoru. Postavlja se testni sustav, popravljaju neki problemi implementacije i analiza trenutni problem simulacije cijelog sustava s RISC-V procesorom na gem5 platformi.
Abstract (english)
Simulation of processors and computer systems enables research in the field of computer architecture and organisation. Several such platforms are available that allow the simulation, emulation, and synthesis of arbitrary instruction set architectures. The structure of the gem5 simulator is presented, the specifics of the RISC-V instruction set and the implementation of the RISC-V ISA in the gem5 simulator are described. A test system is set up, some implementation problems are fixed and the current problem of simulating the whole system with a RISC-V processor on a gem5 platform is analysed
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:358247
Study programmeTitle: Computing
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
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Created on2023-01-13 12:42:05