Analysis of Conducted Electromagnetic Emissions in Integrated Circuits

scientific master's theses

• Title (croatian): Analiza vođenih elektromagnetskih smetnji u integriranim sklopovima
• Author: Vladimir Čeperić
• Mentor: Adrijan Barić (mentor)
• Committee member: Adrijan Barić (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; (Department of Electronics, Microelectronics, Computer and Intelligent Systems); Zagreb
• Defense date and country: 2007, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Electrical Engineering; Electronics
• Universal decimal classification (UDC): 621.3 - Electrical engineering

Abstract

Design of integrated circuits (IC) is a very complex task. One of the most critical steps in the design process is the estimation of electromagnetic compatibility (EMC) of the designed circuit. Electronic equipment has to comply with electromagnetic compatibility standards and integrated circuits are most often the root cause of disturbances in electronic systems. The standards regarding conducted EME (Electromagnetic Emission) and EMI(Electromagnetic Immunity) are measured and simulated as the first step towards achieving EM compatibility. Models suitable for simulations of EM emissions and immunity are developed and their accuracy is assessed. An EMC aware design procedure and effective circuit optimization strategy are demonstrated. An EMC test chip is designed in submicron CMOS technology, processed, measured and the measurement results are compared with simulations in order to demonstrate the validity and accuracy of models and procedures described in this thesis.

Abstract (croatian)

Projektiranje integriranih sklopova vrlo je složen postupak. Jedan od najsloženijih zadataka u projektiranju integriranih sklopova je procjena elektromagnetske kompatibilnosti (EMC). Elektronički proizvodi moraju zadovoljiti standarde za elektromagnetsku kompatibilnost, a najčešći izvor i uzrok smetnji u elektroničkim sustavima su integrirani sklopovi. Da bi se ispitala elektromagnetska kompatibilnost integriranih sklopova u ovom su radu simulirani i mjereni standard za emisiju vođenih elektromagnetskih smetnji i standard za imunitet na vođene elektromagnetske smetnje. Razvijeni su modeli prikladni za simulaciju elektromagnetske emisije i imuniteta, te je procijenjena njihova točnost. Projektiranje elektromagnetski kompatibilnih integriranih sklopova pojednostavljeno je povezivanjem modela potrebnih za analizu elektromagnetske kompatibilnosti s optimizacijskim procedurama. Da bi se procijenila točnost takvih modela, projektirani su, procesirani i izmjereni integrirani sklopovi u submikrometarskoj CMOS tehnologiji i rezultati mjerenja uspoređeni su s rezultatima simulacija.

• Keywords: electromagnetic compatibility (EMC); conducted electromagnetic emissions; electromagnetic immunity; EMC of integrated circuits; circuit optimization; electromagnetic emission source model
• Keywords (croatian): elektromagnetska kompatibilnost (EMC); vođene elektromagnetske smetnje; imunitet na vođene elektromagnetske smetnje; EMC na razini integriranih sklopova; optimizacija sklopova; modeliranje izvora elektromagnetske smetnje
• Language: english
• URN:NBN: urn:nbn:hr:168:335496
• Study programme: Title: Postgraduate master programme in electrical engineering; Study programme type: university; Study level: postgraduate; Academic / professional title: Magistar znanosti elektrotehnike (Magistar znanosti elektrotehnike)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2020-04-08 07:40:31