Akvizicija 1D signala sustavom sažimajućeg očitavanja

master's thesis

• Title (english): Acquisition of 1D Signal Using Compressive Sensing System
• Author: Lucija Oštrić
• Mentor: Ana Sović Kržić (mentor)
• Committee member: Ana Sović Kržić (predsjednik povjerenstva)
• Committee member: Damir Seršić (član povjerenstva)
• Committee member: Goran Molnar (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2019-07-10, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Electrical Engineering

Abstract

U ovom radu bit će opisan realizirani sustav sažimajućeg očitavanja korištenjem razvojnog sustava ZedBoard. Cilj je pokazati kako sustav može raditi sa signalima uzorkovanih puno manjom frekvencijom od Nyquistove. Sustav koristi vanjski šesterokanalni akvizicijski sklop, s kojim je povezan preko FMC konektora. Bit će opisana implementacija sustava u razvojnoj okolini Vivado Design Suite. Sustav ima ulogu osigurati akvizicijskom sklopu pristup mjernoj matrici te očitavanje izmjerenih podataka sa njegovih serijskih izlaza. Mjerna matrica realizirana je kao dvopristupna memorija: jedan pristup omogućuje procesoru upisivanje elemenata matrice, a drugi pristup omogućuje cirkularno čitanje i primjenu množitelja u akvizicijskom sustavu. Očitavanje podataka i privremena pohrana podataka vrši se razvijenim FPGA (engl. Field Programmable Gate Array) međusklopom koji koristi serijsko periferno sučelje (SPI, engl. Serial Peripheral Interface). Za potrebe testiranja bit će razvijen i pomoćni sustav zasnovan na ARM procesorskoj pločici uz korištenje SPI sučelja.

Abstract (english)

In this paper, a synthesized reading system will be described using the ZedBoard development system. The aim is to show how the system can work with a much lower frequency than Nyquist's. The system uses an external six-channel acquisition circuit, which is connected via FMC connectors. It will describe the implementation of the system in the Vivado Design Suite development environment. The system has the role to access the acquisition approach to the metering matrix of reading the measured data with its serial exhibits. The measurement matrix is ​​realized as a two-core memory: one approach has enabled the processing of the input of the matrix elements, and the second approach enables the circular reading and application of multipliers in the acquisition system. Data readout and temporary data storage enable the development of a Field Programmable Gate Array (FPGA) interface that uses a serial peripheral interface (SPI). For testing purposes, an ARM processor based auxiliary system will be developed using the SPI interface.

• Keywords: FPGA; Vivado; Sažimajuće očitavanje; ZedBoard
• Keywords (english): FPGA; Vivado; ZedBoard; compressed sensing
• Language: croatian
• URN:NBN: urn:nbn:hr:168:146226
• Study programme: Title: Electrical Engineering and Information Technology; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije (magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2020-01-07 20:52:55