Povezivanje mreže na čipu s AXI-uređajima

undergraduate thesis

• Title (english): Connecting the Network on Chip with AXI Devices
• Author: Luka Mrković
• Mentor: Daniel Hofman (mentor)
• Committee member: Daniel Hofman (predsjednik povjerenstva)
• Committee member: Josip Knezović (član povjerenstva)
• Committee member: Alen Duspara (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2019-07-12, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing

Abstract

Kao glavni cilj ovog rada, razvijen je NoC-AXI Most. Njegova namjena je omogućiti komunikaciju između modula kompatibilnih s AXI4-Lite protokolom putem mreže na čipu.

AXI4-Lite protokol prenosi podatke putem devetnaest signala podijeljenih u pet podatkovnih kanala. Sinkronizacija u prijenosu postiže se takozvanim VALID/READY rukovanjem koje omogućuje obostranu kontrolu brzine prijenosa.
Podaci kroz mrežu na čipu putuju rascjepkano, u paketima. Ti paketi nazivaju se flitovima.

NoC-AXI Most sastoji se od dva zasebna adaptera. Mrežnog adaptera za Master module - MNA, te mrežnog adaptera za Slave module - SNA. Koji od ta dva adaptera će se koristiti ovisi o ulozi modula u AXI4-Lite transakcijama.
Svaki adapter se sastoji od dva toka podataka - toka zahtjeva i toka odgovora. Tok zahtjeva prenosi zahtjeve za pisanjem iii čitanjem do Master modula prema Slave modulu, dok tok odgovora prenosi odgovore od Slave modula prema Master modulu. Svaki od tokova svakog od adaptera sastoji se od više modula. Glavni i osnovni modul svakog toka je automat s konačnim brojem stanja zadužen za sinkronizaciju komunikacije između adaptera i okoline. Uz njega, tokovi se sastoje od dodatnih modula čije su uloge formatiranje podataka, filtracija podataka i pamćenje povratnih adresa.

Implementaciji sklopa u Verilogu i testiranju pristupljeno je odozdo prema gore - svi moduli implementirani su i testirani individualno prije nego što su spojeni u cjeline. Taj pristup značajno je olakšao proces testiranja. Zadnja stavka u procesu testiranja bilo je postavljanje sklopa u stvarnu okolinu i spajanje sa stvarnim AXI4-Lite modula.

Abstract (english)

The main objective of this paper was to develop the NoC-AXI Bridge. Its purpose is to enable communication between AXI4-Lite-compatible modules through a network on chip.

AXI4-Lite protocol transfers data by means of nineteen signals divided in five channels. Synchronization of the transfer is achieved by using so called VALID/READY handshake process. VALID/READY handshake enables flow control by both parties in a transaction.
Through the network on chip, data travels split in many packets. Those packets are called flits.

NoC-AXI Bridge consists of two separate adapters. Master Network Adapter --- MNA, and Slave Network Adapter --- SNA. Which of those two will be used depends on a role of the module in an AXI4-Lite transaction.
Each adapter consists of two data flows --- Request Flow and Response Flow. The Request Flow transfers read or write requests from the Master to the Slave module, while the Response Flow transfers responses from the Slave to the Master module. Each flow of each adapter consists of multiple modules. The main module of each flow is a finite state machine tasked with synchronizing communication between the adapter and its surroundings. Flows also consist of additional modules that are tasked with formatting data, filtrating data and storing return addresses.

Implementation of the NoC-AXI Bridge in Verilog and its testing was approached from the bottom up --- all the modules were individually implemented and tested before the integration. That approach made testing significantly easier. The final stage of the verification process was placing NoC-AXI Bridge in a real environment and connecting it with real AXI4-Lite-compatible modules.

• Keywords: NoC-AXI Most; AXI4-Lite; VALID/READY rukovanje; mreža na čipu; usmjeritelj; flitovi; mrežni adapter Master modula; mrežni adapter Slave modula; tok zahtjeva; tok odgovora; automati s konačnim brojem stanja; Verilog; AXI VIP
• Keywords (english): NoC-AXI Bridge; AXi4-Lite; VALID/READY Handshake; Network on Chip; router; flits; Master Network Adapter; Slave Network Adapter; Request Flow; Response Flow; Finite State Machines; Verilog; AXI VIP
• Language: croatian
• URN:NBN: urn:nbn:hr:168:506435
• Study programme: Title: Computing; Study programme type: university; Study level: undergraduate; Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2020-01-07 20:38:52