Arhitektura i izvedba dinamički promjenjivog procesora

doctoral thesis

• Title (english): Architecture and implementation of dynamically reconfigurable processor
• Author: Hrvoje Mlinarić
• Mentor: Mario Kovač (mentor)
• Committee member: Mario Žagar (član povjerenstva)
• Committee member: Mario Kovač (član povjerenstva)
• Committee member: Davor Antonić (član povjerenstva)
• Committee member: Vedran Mornar (član povjerenstva)
• Committee member: Damir Kalpić (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; (Department of Control and Computer Engineering); Zagreb
• Defense date and country: 2005, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing; Process Computing
• Universal decimal classification (UDC): 004 - Computer science and technology. Computing. Data processing

Abstract

U ovoj doktorskoj disertaciji pod naslovom „Arhitektura i izvedba dinamički promjenjivog procesora“ predložena je nova arhitektura dinamički promjenjivog procesora koji svoju primjenu ima u izvedbama algoritama za digitalnu obradu signala. Predložena nova arhitektura dinamički promjenjivog procesora projektirana je korištenjem HDL jezika, optimizirana za sklopovsku sintezu, te prototipno izvedena u programibilnoj logici. Predloženi su postupci korištenja novopredložene arhitekture dinamički promjenjivog procesora na algoritmima za digitalnu obradu signala. Korištenjem novopredložene arhitekture dinamički promjenjivog procesora smanjena je potrebna logika za izvedbu algoritama za digitalnu obradu signala i povećana performansa procesora. Predložen je i razvijen postupak promjene dinamički promjenjivog procesora koji omogućuje istovremeno izvođenje trenutne funkcije dinamički promjenjivog sklopa i učitavanje nove funkcionalne konfiguracije dinamički promjenjivog sklopa.

Abstract (english)

In this PhD dissertation "Architecture and implementation of dynamically reconfigurable processor" author suggests a new architecture of dynamically reconfigurable processor that can be used in execution of digital signal processing algorithms. Suggested architecture of dynamically reconfigurable processor is designed using HDL language, optimized for hardware synthesis and verified as prototype designed in programmable logic. New procedures for use of dynamically reconfigurable digital signal processing processor are suggested. Use of proposed architecture decreases amount of needed logic for digital signal processing algorithm implementation, at the same time increasing processor performance. Also, a set of procedures for dynamic change of processor is proposed, that enables execution of current processor functions and loading of new functional configuration of processor at the same time.

• Keywords: Dinamički promjenjivi procesor; programibilna logika; FPGA; digitalna obrada signala; multimedija; zbrajalo; množilo; arhitektura procesora
• Keywords (english): Dynamically reconfigurable processor; reconfigurable computing; FPGA; multimedia; digital signal processing; processor architectures
• Language: croatian
• URN:NBN: urn:nbn:hr:168:398409
• Study programme: Title: Computer Science; Study programme type: university; Study level: postgraduate; Academic / professional title: Doktor znanosti (Doktor znanosti)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2019-07-04 07:55:23