Moderne komunikacije zasnovane su na velikom broju standarda koji se stalno nadograđuju. Iz tog razloga komunikacijski sustavi postaju sve kompleksniji, a njihova nadogradnja je u mnogim slučajevima nemoguća. Posljednjih godina ovaj problem rješava se prijelazom u digitalnu domenu, te korištenjem postupaka za digitalnu obradu signala. Ovakav pristup izražen je kod modernih prijamnika, kod kojih se nastoji minimizirati ulazno analogno sklopovlje, te digitalnu obradu signala što više približiti anteni. Prijamnici s takvom arhitekturom približavaju se takozvanoj kanonskoj arhitekturi. Ovaj rad bavi se postupcima za digitalnu obradu signala koji se susreću u programski definiranim prijamnicima te njihovom učinkovitom implementacijom na programabilnim logičkim poljima (FPGA). U okviru rada razvijen je sustav za prijam kompleksne ovojnice radiofrekvencijskih signala optimiran za implementaciju na programabilnim logičkim poljima. Pritom je širina riječi svakog gradivnog bloka optimirana obzirom na zauzeće sklopovlja te odnos signala i šuma primljenog signala. Kao dio ovog prijamnika, opisana je arhitektura digitalnog sustava za automatsku regulaciju pojačanja signala visoke dinamike, izvedena bez množila opće namjene. Ovaj podsustav predviđen je za rad s kompleksnim signalima te se stoga nadovezuje na podsustav za prijam kompleksne ovojnice. Opisani prijamnik pogodan je za prijam signala moduliranih analognim i digitalnim modulacijskim postupcima. Za demodulaciju signala moduliranih digitalnim postupcima razvijene su arhitekture dvaju procesora s mekom jezgrom. Ove arhitekture optimirane su za izvođenje skalarnog produkta kompleksnih vektora, te spajanje procesora u lanac za obradu signala. Predviđene su za implementaciju na Xilinx FPGA sklopovlju. U okviru rada razmatrani su i postupci za smanjivanje utjecaja nelinearnosti prisutnih u analogno-digitalnim pretvornicima. U tom kontekstu predložen je digitalni generator Gaussovog šuma zadane spektralne gustoće snage, izveden bez množila opće namjene.
|Abstract (english)|| |
The last decade is characterized with intensive penetration of digital technologies in all technical disciplines. It is especially visible in signal processing in which there is a tendency of moving more and more parts from analog to digital domain. Typical examples of such trend are communication systems. Modern communications are based on large number of standards that are constantly upgrading. The systems are expected to follow these changes. Therefore, they become more complex, their maintenance more expensive, and the upgrade sometimes impossible. The use of digital signal processing makes design more flexible thus solving these problems. Digital signal processing has also become unavoidable part of modern receivers in which the main task is to minimize analog circuitry and move digital signal processing as close to the antenna as possible within the current state of technology. This work considers signal processing in high dynamic range software defined receivers. The architecture of the system for receiving of complex envelope of radio signals is developed, which is optimized for the implementation on field programmable gate arrays (FPGA). As a part of this system, the architecture of an automatic gain control is proposed which operates with high dynamic range signals. It is realized without the use of general purpose multipliers. These systems form digital front-end of a high dynamic range software defined receiver suitable for receiving signals modulated with analog as well as with digital modulations. For the demodulation of latter signals, two soft-core processor architectures are developed. Furthermore, the methods for mitigation of undesired effects caused by nonlinearities in analog to digital converters are also considered. In this context, a multiplierless realization of the colored noise generator is proposed. This generator can generate Gaussian noise with prescribed power spectral density. In the second chapter, the basic concepts and well-known receiver architectures are briefly described. The attention is paid to architectures that are used in software defined receivers. Lowpass and bandpass sampling is described, together with processing of the complex envelope. Furthermore, an overview of papers is given which describes the development of software defined receivers. At the end, significant papers are selected which describe the implementation of software defined receivers on field programmable gate arrays. The third chapter describes the architecture of the proposed receiver. The receiver comprises two subsystems, one implemented in analog and another implemented in digital technology. The analog subsystem is realized using standard high performance integrated circuits. On the other hand, the digital subsystem is completely realized in one integrated circuit. Xilinx FPGA devices are chosen as the implementation platform for digital subsystem. In this chapter, basic blocks of both subsystems are identified. They are described in details in the rest of the dissertation. The fourth chapter describes the digital system for receiving of the complex envelope. This system is based on the direct conversion architecture. The received signal is transposed into the baseband using complex mixing. The complex exponential function is generated by using numerically controlled oscillator. After the complex mixing, the decimation is performed by using a cascaded integrator-comb (CIC) decimator. After the CIC decimator, the desired channel is filtered out by using the complex FIR filter. For every building block the word lengths are optimized with respect to hardware usage and signal to noise ratio of the received signal. The described system is entirely implemented as digital. It is optimized for the implementation on Xilinx FPGA devices. In the fifth chapter an automatic gain control (AGC) is described. This system is suitable for processing of complex signals. Therefore, it can be placed after the system for receiving the complex envelope. The AGC is completely implemented digitally without the need of general purpose multipliers, which results in an efficient implementation. The system’s robustness is achieved by using a feed forward design. The AGC outputs the signal which is normalized to its maximum value. The sixth and seventh chapter describe the realized soft-core processors whose main feature is digital signal processing. Their architectures are optimized for calculating the inner product of complex-valued vectors. Furthermore, they can be easily connected to form signal processing chain. The first processor has a simple architecture whose main part consists of a complex arithmetic-logic unit and three complex registers. The second processor, besides the complex arithmetic unit and complex registers, has a separate arithmetic-logic unit that is used for processing real-valued scalars. This unit has its own register bank, consisting of eight real-valued registers. Both processors are optimized for the implementation on Xilinx FPGA devices. In the eighth chapter the receiver’s analog front-end is considered. It consists of circuitry for analog preprocessing and the analog to digital converter (ADC). Additionally, it includes the circuitry for adding colored noise to the signal before the ADC. The added noise is used for mitigation of undesired effects caused by the nonlinearities which are present in the converter. As a noise source, a digital colored noise generator is proposed, which is realized without general purpose multipliers. The generated noise has a Gaussian distribution and prescribed power spectral density. The receiver described follows the trend of minimization of analog circuitry in software defined receivers, thus following well-known Mitola's concept. The major part of the digital subsystem is the receiver itself. However, the digital subsystem can also contain the circuits which improve the properties of the analog subsystem. Here, it was illustrated by the design of the noise generator. FPGA platform proved to be suitable for the integration of the entire digital subsystem. It was shown by straight-forward implementation of the algorithms, as well as by the implementation of generic hardware. The former is illustrated by the implementation of the subsystem for generation of the complex envelope, the AGC, and the noise generator. The latter is illustrated via the design of dedicated processors. The entire digital subsystem occupies acceptable part of an FPGA device of middle complexity, resulting in receiver's low cost. Receiver's efficiency is accomplished by two approaches. The subsystem for receiving the complex envelope and the processors are realized assuming the platform contains the embedded memories and multipliers. On the other hand, the AGC and the noise generator are realized by using only elementary operations. In this sense they are also suitable for the use in application specific integrated circuits.
The receiver described is primarily designed for the receivers using lowpass sampling. However, its digital subsystems can be easily adopted for bandpass sampling.