Projektiranje sklopovskih blokova analogno-digitalnog pretvornika sa sukcesivnom aproksimacijom u 0.35 um CMOS tehnologiji

master's thesis

• Title (english): Design of the circuit blocks for successive approximation register analog to digital converter in 0.35 um CMOS technology
• Author: Tomislav Miletić
• Mentor: Marko Koričić (mentor)
• Committee member: Marko Koričić (predsjednik povjerenstva)
• Committee member: Željko Butković (član povjerenstva)
• Committee member: Tomislav Suligoj (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2014-07-11, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Electrical Engineering

Abstract

U ovom radu projektirani su sklopovski blokovi SAR A/D pretvornika korištenjem 0.35 µm CMOS tehnologije. Za postizanje željenih specifikacija analizirana je konfiguracija S&H sklopa s mogućnosti poništavanja napona pomaka pojačala. U S&H sklopu korištene su CMOS sklopke. Komparator je projektiran u konfiguraciji pretpojačala i bistabila radi postizanja vrlo brzog odziva. Kontrolna logika koja se sastoji od kružnog brojila i posmačnog registra ostvarena je asinkronim D bistabilima. Nadalje, projektirani D/A pretvornik s raspodijeljenim nabojem sadrži kapacitivnu mrežu i ugrađeni S&H sklop. Blokovi su projektirani za tipičan tehnološki proces i radne uvjete na razini električke sheme. Postignute su karakteristike koje zadovoljavaju primjenu u SAR ADP-u razlučivosti 12 bita i frekvencije uzorkovanja 1 MS/s.

Abstract (english)

In this thesis the circuit blocks of an SAR A/D converter were designed in 0.35 µm CMOS technology. To achieve the target specifications, a configuration of an S&H circuit with the cancellation of amplifier offset voltage was analysed. CMOS transmission gates were used in the S&H circuit. The comparator was designed in a configuration of a preamplifier and a latch, in order to achieve a very short response time. The control logic consisting of ring counter and shift register was realised using asynchronous D-type flip-flops. Moreover, designed charge redistribution D/A converter has capacitive network and inherent S&H circuit. The Blocks were designed for typical process corners on the schematic level. The required performance for the application in a 12-bit 1 MS/s SAR ADC was achieved.

• Keywords: S&H sklop; CMOS sklopka; pretpojačalo; bistabil; komparator; kontrolna logika; D/A pretvornik
• Keywords (english): S&H circuit; CMOS transmission gate; preamplifier; latch; comparator; control logic; D/A converter
• Language: croatian
• URN:NBN: urn:nbn:hr:168:497222
• Study programme: Title: Electrical Engineering and Information Technology; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije (magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2019-03-19 13:43:17