Smanjivanje šuma u digitalnim slikama upotrebom sklopova FPGA

master's thesis

• Title (english): Noise Reduction in Digital Images with FPGA Devices
• Author: Dino Šporčić
• Mentor: Mario Cifrek (mentor)
• Committee member: Mario Cifrek (predsjednik povjerenstva)
• Committee member: Igor Krois (član povjerenstva)
• Committee member: Željka Lučev Vasić (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2017-07-05, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing

Abstract

Brza obrada digitalne slike zahtjeva korištenje tehnologije koja može što veću količinu podataka obraditi u što kraćem vremenu. Paralelna obrada velike količine podataka je ono što povezuje obradu digitalne slike i FPGA sklopova. Za kvalitetnu obradu slike potrebno je imati što kvalitetniju sliku. Smanjivanje šuma je jedan od faktora poboljšanja kvalitete slike. U ovom radu opisan je jedan takav algoritma implementiran u VHDL-u. Algoritam se temelji na usmjerenom zaglađivanju FIR filtrom uz smjer odabran tako da čuva bridove. Bridovi se detektiraju uporabom Sobelovih operatora. Simulacija takve metode smanjivanja šuma provedena je u programskom jeziku Python. Kada je simulacija počela davati dobre rezultate, algoritam je implementiran u jeziku VHDL u tehnološki neovisnom formatu (RTL). Implementirana komponenta radi s formatom YCbCr (4:4:4) u preciznosti od 8 do 12 bita, a smanjivanje šuma provodi se samo nad luminantnom komponentom. Za svaku implementaciju davane su kvalitativne usporedbe slika s uklanjanjem šuma i bez njega. Komponenta je sintetiziran i implementiran na Lattice FPGA sklopu uz utrošak od samo 5 množila i 22 blok RAM memorije.

Abstract (english)

Fast processing of a digital image requires the use of technology that can handle as much data as possible in the shortest possible time. Parallel processing of large amounts of data is what connects the processing of digital images and FPGA devices. For high quality image processing, it is necessary to have a picture in highest quality as possible. Reducing noise is one of the factors for improving image quality. This paper describes one such algorithm implemented in VHDL. The algorithm is based on directional smoothing with a FIR filter along the direction chosen to keep the edges. Edges are detected using Sobel operators. Simulation of such noise reduction method was done in the Python programming language. When the simulation started to provide good results, the algorithm was implemented in VHDL in technologically independent format (RTL). The implemented component works with YCbCr format (4: 4: 4) in 8 to 12 bit precision, and noise reduction is performed only over the luminance component. For each implementation, qualitative comparison of image with and without noise removal was provided. The component was synthesized and implemented on the Lattice FPGA device with a consumption of only 5 multiplier and 22 block RAMs.

• Keywords: uklanjanje šuma; digitalna slika; VHDL; Sobelov operator; filtar za zaglađivanje; FPGA; obrada digitalne slike; obrada video signala; Python
• Keywords (english): Noise reduction; digital image; VHDL; Sobel operator; smoothing filter; FPGA; digital image processing; video signal processing; Python
• Language: croatian
• URN:NBN: urn:nbn:hr:168:860721
• Study programme: Title: Computing; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2019-03-14 01:23:44