Utjecaj zaštite od elektrostatskog pražnjenja (ESD) na ulazno-izlazno sučelje čipleta

master's thesis

• Title (english): Impact of ESD protection on chiplet I/O
• Author: Mihael Krilčić
• Mentor: Tomislav Marković (mentor)
• Committee member: Tomislav Marković (predsjednik povjerenstva)
• Committee member: Tvrtko Mandić (član povjerenstva)
• Committee member: Vladimir Čeperić (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2024-09-20, Croatia

Abstract

Nastavkom trenda minijaturizacije kod poluvodičke industrije, skaliranje tranzistora dostiže svoje fizičke granice. Potražnja za većom snagom i boljim performansama dovodi do nelinearnog rasta troškova lithografije u odnosu na površinu čipova. Kao rezultat, industrija usvaja paradigmu Ko-Optimizacije Dizajna i Tehnologije (DTCO) te Ko-Optimizacije Sustava i Tehnologije (STCO), gdje se iskorištava treća dimenzija
uređaja i integrirane heterogene arhitekture čipova za očuvanje daljnjeg napretka.... More Ova teza istražuje utjecaj ugradnje zaštite od elektrostatskog pražnjenja (ESD) u ulazno-izlazno (I/O) sučelje unutar Unaprijeđenih 2D i 3D integriranih arhitektura, fokusirajući se na prvu generaciju FinFET uređaja.
Korištenjem VF-TLP TDT mjerne tehnike i analize S-parametara, ovo istraživanje procjenjuje vrijednosti dodanog kapaciteta i površine različitih ESD zaštitnih uređaja skaliranih za razne nivoe CDM zaštite. Analiza obuhvaća samostalnu ESD zaštitu, samostalne I/O krugove i I/O krugove s ESD zaštitom, radi procjene razine CDM zaštite u svakom slučaju. Rezultati pokazuju da učinkovitost ESD zaštite ovisi o maksimalnim naponskim vrijednostima oksida upravljačke elektrode prijemnika i napona odvoda odašiljača. Dodatno, istraživanje pokazuje veću razinu otpornosti pMOS tranzistora u odnosu na nMOS tranzistore. Iako je ESD zaštita potrebna samo pri spajanju čipleta, njezina stalna prisutnost povećava kapacitet, što uzrokuje kompromis između integriteta signala, potrošnje energije i brzine prijenosa podataka.
Istraživanje dodatno proučava trend smanjenja CDM razina zaštite dok se razmak izneđu prijenosnih linija smanjuje, analizirajući vrijednosti dodanog kapacita I površine koje su potrebne za postizanje trenutnih i budućih standarda zaštite, kao što je navedeno u UCIe ili u White Paper 2 specifikaciji. Zaključak pokazuje značajne compromise između učinkovitosti ESD zaštite, dodatnog kapaciteta i površine, naglašavajući izazov uravnoteženja nivoa zaštite i performansi u budućim dizajnima čipleta. Less

Abstract (english)

As the semiconductor industry continues to push the boundaries of miniaturization, transistor scaling hits physical limits. The demand for greater power and chip performance drives a non-linear increase in the cost versus area trend of lithography and patterning. Consequently, the industry is transitioning to Design-Technology Co-Optimization (DTCO) and System-Technology Co-Optimization (STCO) models, where utilizing the devices’ third dimension and integrated heterogeneous architectures help... More sustain further progress. This thesis investigates the impact of incorporating electrostatic discharge (ESD) protection in I/O circuits within Enhanced 2D and 3D integrated architectures, focusing on first-generation FinFET devices.
Using VF-TLP TDT Kelvin measurement technique and S-parameter analysis, this research evaluates the capacitance and layout penalties of various ESD protection devices scaled for different CDM (Charged Device Model) protection levels. The study covers stand-alone ESD protection devices, stand-alone I/O drivers and I/O drivers combined with ESD protection to assess CDM protection levels in each case. Results show that ESD protection effectiveness is constrained by the receiver gate-oxide and the transmitter drain-body breakdown voltages. Additionally, the study finds pMOS transistors exhibit greater robustness compared to nMOS transistors in both driver designs. Moreover, while ESD protection is necessary only during the chiplet bonding process, its continued presence introduces additional capacitance, leading to compromises between signal integrity, power consumption and data rates.
The study further explores the industry trend toward lowering CDM protection levels as pitch continues to shrink, examining how much capacitance and area are necessary to meet current and future CDM protection standards, such as those outlined by the UCIe Specification or White Paper 2. Findings reveal significant compromises between ESD protection effectiveness, added capacitance and layout area, highlighting the challenge of balancing protection and performance in future chiplet designs. Less

• Keywords: Elektrostatsko Pražnjenje (ESD); ESD Zaštita; Čipleti; I/O Dizajn; FinFET Uređaji; Ko-Optimizacija Dizajna i Tehnologije (DTCO); Ko-Optimizacija Sustava i Tehnologije (STCO); Unaprijeđene 2D i 3D Integrirane Arhitekture; VF-TLP TDT; CDM Razina Zaštite
• Keywords (english): Electrostatic Discharge (ESD); ESD Protection; Chiplets; I/O Design; Fin-FET Devices; Design-Technology Co-Optimization (DTCO); System-Technology Co-Optimization (STCO); Pitch Scaling; Enhanced 2D and 3D Integrated Architectures; VF-TLP TDT; CDM (Charged Device Model) Protection Levels
• Language: english
• URN:NBN: urn:nbn:hr:168:694089
• Study programme: Title: Electrical Engineering and Information Technology; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije (magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Embargoed access; Embargo expiration date: 2025-09-20
• Created on: 2025-03-12 10:31:30