Izvedba sustava sa FRISC-V procesorom

undergraduate thesis

• Title (english): Implementation of FRISC-V processor system
• Author: Petra Kelković
• Mentor: Mario Kovač (mentor)
• Committee member: Mario Kovač (član povjerenstva)
• Committee member: Hana Ivandić (član povjerenstva)
• Committee member: Ana Šikić (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2024-06-26, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing

Abstract

Pod vodstvom prof. Maria Kovača, studenti su razvili FER-ovu inačicu 32-bitnog FRISC-V procesora. Ovim radom unaprijeđen je FRISC-V procesor, omogućujući njegovu implementaciju na Xilinx FPGA pločicu te samostalno upravljanje periferijama. Upravljački modul protočne strukture je unaprijeđen te može uspješno detektirati i rješavati podatkovne i upravljačke hazarde u protočnoj strukturi. Optimiziran je memorijski modul i dodan sustav za signalizaciju kraja programa. Razvijen je i modul 8-bitnog izlaznog registra za upravljanje periferijama. Sustav je integriran s ARM Cortex-A9 dvojezgrenim procesorom, te je jednostavno programiranje i korištenje omogućeno putem razvijenih aplikacija.

Abstract (english)

Under the guidance of prof. Mario Kovač, students developed FER's version of a 32-bit FRISC-V processor. This thesis enhanced the FRISC-V processor, enabling its implementation on a Xilinx FPGA board and independent control of peripherals. The control module of the instruction pipeline was improved and is now capable of successfully detecting and resolving data and control hazards within the pipeline. The memory module was optimized, and a system for end-of-program signaling was added. An 8-bit output register module was also developed for peripheral management. The system was integrated with a dual-core ARM Cortex-A9 processor, and simple programming and usage were facilitated through the developed applications.

• Keywords: RISC-V arhitektura; RV32I ISA; FRISC-V procesor; protočna struktura; izlazni registar; signal za kraj programa
• Keywords (english): RISC-V architecture; RV32I ISA; FRISC-V processor; instruction pipeline; output register; end-of-program signal
• Language: croatian
• URN:NBN: urn:nbn:hr:168:463041
• Study programme: Title: Computing; Study programme type: university; Study level: undergraduate; Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2024-10-12 21:02:37