Razvoj i integracija edukacijskog računalnog sustava s procesorom arhitekture RISC-V u programabilnoj logici

master's thesis

• Title (english): Development and integration of an educational computing system with RISC-V processor in programmable logic
• Author: Filip Horvat
• Mentor: Josip Knezović (mentor)
• Committee member: Josip Knezović (član povjerenstva)
• Committee member: Danko Basch (član povjerenstva)
• Committee member: Igor Čavrak (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2024-07-17, Croatia

Abstract

RISC-V je nova ISA, koja je jednostavna za naučiti. Na FER-u se koristi za učenje Arhitekture Računala izvršavanjem programa u zbirnom jeziku na RISC-V sustavu u simulatoru SSPARCSS. Cilj ovog projekta je nadopuniti iskustvo učenja stvaranjem fizičkog hardvera za izvršavanje programa koristeći ZYNQ SoC. Prikazane su osnove RISC-V ISA, nakon čega je opisana implementacija sustava u tri dijela: hardver, softver na strani pločice i računalni softver. Hardver, implementiran pomoću Vivado IP Integrator-a sadrži memoriju, periferiju i PicoRV32 RISC-V meku jezgru koja se koristi za izvršavanje programa. Softver na strani ploče, pisan u C-u, se izvšava na ZYNQ Processing System-u i koristi se za kontrolu ostatka SoC-a te komunikaciju s računalom pomoću UART-a. Računalni softver, pisan u Rust-u, se izvršava na računalu i pruža API visoke razine za komunikaciju između simulatora i SoC-a.
Projekt je dovršen i hardver radi, međutim, potrebno je još rada da bi se uskladio sa simulatorom.

Abstract (english)

RISC-V is a new, clean-slate ISA that is simple to learn.At FER, it is used to teach Computer Architecture by running assembly programs on a RISC-V system in a simulator called SSPARCSS. This project aims to complement the learning experience by creating physical hardware to run the programs using a ZYNQ SoC. The basics of RISC-V are presented, after which the system's implementation is described in three parts: hardware, board-side software and computer-side software. The hardware, implemented using Vivado's IP Integrator contains memory, peripherals and a PicoRV32 RISC-V soft-core used to execute programs. The board-side software, written in C, runs on the ZYNQ Processing System and is used to control the rest of the SoC and communicate with the computer using UART. The computer-side software, written in Rust, runs on a computer and provides a high-level API for communication between the simulator and the SoC. The project is completed and the hardware works, however, more work is needed to bring it to parity with the simulator.

• Keywords: RISC-V; ISA; FPGA; SoC; ZYNQ
• Keywords (english): RISC-V; ISA; FPGA; SoC; ZYNQ
• Language: english
• URN:NBN: urn:nbn:hr:168:625015
• Study programme: Title: Computing; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2024-10-12 20:48:28