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undergraduate thesis
FPGA implementacija Huffmanovog dekodiranja JPEG dekodera
2024. urn:nbn:hr:168:376335
Fodor, Fran
University of Zagreb
Faculty of Electrical Engineering and Computing

Cite this document

Fodor, F. (2024). FPGA implementacija Huffmanovog dekodiranja JPEG dekodera (Undergraduate thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:376335

Fodor, Fran. "FPGA implementacija Huffmanovog dekodiranja JPEG dekodera." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2024. https://urn.nsk.hr/urn:nbn:hr:168:376335

Fodor, Fran. "FPGA implementacija Huffmanovog dekodiranja JPEG dekodera." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2024. https://urn.nsk.hr/urn:nbn:hr:168:376335

Fodor, F. (2024). 'FPGA implementacija Huffmanovog dekodiranja JPEG dekodera', Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 07 April 2025, https://urn.nsk.hr/urn:nbn:hr:168:376335

Fodor F. FPGA implementacija Huffmanovog dekodiranja JPEG dekodera [Undergraduate thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2024 [cited 2025 April 07] Available at: https://urn.nsk.hr/urn:nbn:hr:168:376335

F. Fodor, "FPGA implementacija Huffmanovog dekodiranja JPEG dekodera", Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2024. Available at: https://urn.nsk.hr/urn:nbn:hr:168:376335

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Metadata
TitleFPGA implementacija Huffmanovog dekodiranja JPEG dekodera
Title (english)FPGA implementation of Huffman decoding in JPEG decoder
AuthorFran Fodor
MentorDaniel Hofman (mentor)
Committee memberDaniel Hofman (član povjerenstva)
Committee memberLuka Mrković (član povjerenstva)
Committee memberStipe Mišković (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2024-07-02, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Abstract
Implementacija JPEG dekodera na FPGA PYNQ-Z1 pločici pisana je u C++-u i sintetiziran pomoću Vitis HLS-a. HLS automatizira implementaciju C/C++ koda u Verilog koji se stavlja na pločicu. Upravljanje pločicom ostvareno je pomoću Jupyter Notebook-a. Preko Jupyter Notebook-a šalju se potrebni podatci i primaju dekodirane vrijednosti. Također je provedena usporedba dekodiranja na FPGA, ARM procesoru na pločici, na procesoru Ryzen 7 5700U te na procesoru i9-12900k.
Abstract (english)
Implementation of JPEG decoder on PYNQ-Z1 FPGA board written in C++ and synthesized using Vitis HLS. HLS automatically translates C++ code into Verilog code which is used to program the functionality of board. Communication with the board is achieved using Jupyter Notebook through which data is sent and received. Comparison is done using the board, ARM CPU on the board, Ryzen 7 5700U CPU and i9-12900k CPU.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:376335
Study programmeTitle: Computing
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
Access conditionsOpen access
Terms of useLicence In copyright icon
Public note
Created on2024-10-12 20:34:51
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