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master's thesis
Implementacija procesora RISC-V s priručnom memorijom u tehnologiji FPGA
2023. urn:nbn:hr:168:671904
Harmina, Tomislav
University of Zagreb
Faculty of Electrical Engineering and Computing

Cite this document

Harmina, T. (2023). Implementacija procesora RISC-V s priručnom memorijom u tehnologiji FPGA (Master's thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:671904

Harmina, Tomislav. "Implementacija procesora RISC-V s priručnom memorijom u tehnologiji FPGA." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2023. https://urn.nsk.hr/urn:nbn:hr:168:671904

Harmina, Tomislav. "Implementacija procesora RISC-V s priručnom memorijom u tehnologiji FPGA." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2023. https://urn.nsk.hr/urn:nbn:hr:168:671904

Harmina, T. (2023). 'Implementacija procesora RISC-V s priručnom memorijom u tehnologiji FPGA', Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 30 November 2024, https://urn.nsk.hr/urn:nbn:hr:168:671904

Harmina T. Implementacija procesora RISC-V s priručnom memorijom u tehnologiji FPGA [Master's thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2023 [cited 2024 November 30] Available at: https://urn.nsk.hr/urn:nbn:hr:168:671904

T. Harmina, "Implementacija procesora RISC-V s priručnom memorijom u tehnologiji FPGA", Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2023. Available at: https://urn.nsk.hr/urn:nbn:hr:168:671904

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Metadata
TitleImplementacija procesora RISC-V s priručnom memorijom u tehnologiji FPGA
Title (english)FPGA implementation of a RISC-V processor with cache memory
AuthorTomislav Harmina
MentorDaniel Hofman (mentor)
Committee memberDaniel Hofman (član povjerenstva)
Committee memberHrvoje Mlinarić (član povjerenstva)
Committee memberDanko Basch (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2023-07-04, Croatia
Abstract
U ovom diplomskom radu napravljena je RISC-V jezgra sa priručnim memorijama i mogućnosti izvršavanja instrukcija izvan programskog redosljeda. Opisana je arhitektura jezgre, okolnog sustava i djelovi korištenog koda. Izgrađena jezgra je ispitana koristeći postojeće programsko okruženje za RISC-V procesore. Programi korišteni za ispitivanje procesora uključuju Dhrystone, Coremark i Diskretna Kosinusna Transformacija (DCT). Sintetizirana jezgra ispitana je na Digilent Nexys A7 pločici sa Xilinx Artix-7 100T FPGA-om.
Abstract (english)
This paper describes the implementation of a RISC-V core which supports caches and Out-of-Order execution. The paper describes the architecture of the built core and the surrounding system which enables the use of the core. The core has been tested using an existing RISC-V software library. Programs used to test the core include Dhrystone, Coremark and Discrete Cosine Transform (DCT). Synthesized core has been tested on a Digilent Nexys A7 board with Xilinx Artix-7 100T FPGA.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:671904
Study programmeTitle: Computing
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
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Created on2024-03-28 07:46:48