Dizajn gradivnih komponenti procesora arhitekture RISC-V za programabilnu logiku

master's thesis

• Title (english): Design of RISC-V ISA Processor Components for Programmable Logic Implementation
• Author: Maksimilijan Marošević
• Mentor: Josip Knezović (mentor)
• Committee member: Josip Knezović (član povjerenstva)
• Committee member: Mario Kovač (član povjerenstva)
• Committee member: Igor Čavrak (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2023-07-12, Croatia

Abstract

Programiranje u asembleru vještina je kojom se stječe razumijevanje arhitekture računala. Iako se asemblerski kod može pisati u simulatoru, rad na sklopovlju daje dublju dimenziju stjecanju te vještine. Programabilna logika, poput FPGA, idelana je za ovakve slučajeve, jer se na istom sklopovlju mogu ostvariti implementacije raznih jezgara bez potrebe za izradom stvarnog procesora. Ovaj rad implementira jezgru arhitekture RISC-V u jeziku SystemVerilog. RISC-V je izabran zbog sve većeg utjecaja u industriji i zbog svoje modularnosti koja omogućuje implementaciju manjeg skupa instrukcija. Implementacija je verificirana Univerzalnom verifikacijskom metodologijom, industrijskim standardom za provjeru valjanosti sklopovskog dizajna. Napisani su testovi u tri razine - pojedinačni, integracijski, sustavski - te je njima utvrđena ispravnost dizajna.

Abstract (english)

Assembly programming is a vital skill in understanding computer architecture. Although assembly code can be written in a simulator, working with hardware gives additional depth to acquiring the skill. Programmable logic, such as FPGA, is ideal for cases like this since it's possible to realise different CPU core implementations on the same circuit board without the need to manufacture actual processor dies. This paper implements a RISC-V core in SystemVerilog. RISC-V was chosen because of its growing influence in the industry and its modularity, which enables implementation of only a small instruction set. The implementation is verified with Universal Verification Methodology, an industry standard used to prove hardware design correctness. Three stages of tests were written - unit tests, integration tests and system tests - which were used to verify the design.

• Keywords: RISC-V; SystemVerilog; HDL; FPGA; arhitektura računala; UVM; verifikacija
• Keywords (english): RISC-V; SystemVerilog; HDL; FPGA; computer architecture; UVM; verification
• Language: croatian
• URN:NBN: urn:nbn:hr:168:977111
• Study programme: Title: Computing; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2023-10-11 09:43:09