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undergraduate thesis
Dizajn gradivnih komponenti procesora arhitekture RISC-V za programabilnu logiku
2022. urn:nbn:hr:168:253299
Mikulić, Josip
University of Zagreb
Faculty of Electrical Engineering and Computing

Cite this document

Mikulić, J. (2022). Dizajn gradivnih komponenti procesora arhitekture RISC-V za programabilnu logiku (Undergraduate thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:253299

Mikulić, Josip. "Dizajn gradivnih komponenti procesora arhitekture RISC-V za programabilnu logiku." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2022. https://urn.nsk.hr/urn:nbn:hr:168:253299

Mikulić, Josip. "Dizajn gradivnih komponenti procesora arhitekture RISC-V za programabilnu logiku." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2022. https://urn.nsk.hr/urn:nbn:hr:168:253299

Mikulić, J. (2022). 'Dizajn gradivnih komponenti procesora arhitekture RISC-V za programabilnu logiku', Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 06 December 2024, https://urn.nsk.hr/urn:nbn:hr:168:253299

Mikulić J. Dizajn gradivnih komponenti procesora arhitekture RISC-V za programabilnu logiku [Undergraduate thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2022 [cited 2024 December 06] Available at: https://urn.nsk.hr/urn:nbn:hr:168:253299

J. Mikulić, "Dizajn gradivnih komponenti procesora arhitekture RISC-V za programabilnu logiku", Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2022. Available at: https://urn.nsk.hr/urn:nbn:hr:168:253299

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Metadata
TitleDizajn gradivnih komponenti procesora arhitekture RISC-V za programabilnu logiku
Title (english)Design of RISC-V ISA Processor Components for Programmable Logic Implementation
AuthorJosip Mikulić
MentorJosip Knezović (mentor)
Committee memberJosip Knezović (član povjerenstva)
Committee memberDanko Basch (član povjerenstva)
Committee memberIgor Čavrak (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2022-09-13, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Abstract
U ovom radu dan je pregled RISC-V specifikacije naredaba procesora, te pregled programskog paketa SSPARCSS. Tema ovog rada je proširenje sustava SSPARCS dodavanjem sustava za automatizaciju testiranja asemblerskih programa u svrhu razvoja sklopovske izvedbe procesora arhitekture RISC-V.
Abstract (english)
This thesis contains a survey of RISC-V ISA and SSPARCSS simulation program package. The focus of the thesis was the implementation of automated testing system of assembler programs into SSPARCSS for automated verification of RISC-V hardware implementation.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:253299
Study programmeTitle: Computing
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
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Created on2023-01-15 10:51:31