Izvedba protočne strukture FRISC-V procesora

undergraduate thesis

• Title (english): Implementation of FIRSC-V pipeline
• Author: Matej Grzunov
• Mentor: Mario Kovač (mentor)
• Committee member: Mario Kovač (član povjerenstva)
• Committee member: Josip Knezović (član povjerenstva)
• Committee member: Daniel Hofman (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2022-07-01, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing

Abstract

U sklopu ovog završnog rada dizajnirana je, izvedena i verificirana protočna struktura FRISC-V 32-bitne procesorske jezgre, koja može izvršavati naredbe RV32I podskupa naredbi RISC-V arhitekture skupa naredbi. Protočna struktura sastavljena je od 5 razina koje omogućavaju dohvaćanje podataka iz memorije, njihovu obradu, te pohranu nazad u memoriju. Proučene su vrste hazarda koje se mogu pojaviti, te njihovo razrješavanje kroz izvedbu harvardske arhitekture pristupa memoriji, upravljačke signale za izazivanje internog zastoja protočne strukture, i ubacivanje mjehurića u protočnu strukturu. Ispitivanje protočne strukture provedeno je na malim programskim odsječcima, provjerom postupne promjene stanja registara, podatkovne memorije i internih signala.

Abstract (english)

The core part of this thesis was the design, implementation, and verification of the FRISC-V processor core’s instruction pipeline, which supports the execution of instructions defined by the RV32I subset of the RISC-V instruction set architecture. The 5-stage instruction pipeline with in-order instruction execution supports reading data from the data memory, doing various calculations on it, and then writing it back into memory. The potential hazard situations were ascertained and resolved by designing the processor core with the Harvard memory access architecture in mind, creating specialized stall logic in the pipeline, and by injecting pipeline bubbles. The pipeline was tested by running small, assembled, bare machine programs, all the while inspecting the contents of registers, the data memory, and internal signal states.

• Keywords: RISC-V; arhitektura skupa naredbi (ISA); procesor s mekom jezgrom; protočna struktura s 5 razina; razrješavanje hazarda
• Keywords (english): RISC-V; instruction set architecture (ISA); softcore processor; 5-stage instruction pipeline; hazard resolution
• Language: croatian
• URN:NBN: urn:nbn:hr:168:133848
• Study programme: Title: Computing; Study programme type: university; Study level: undergraduate; Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2023-01-15 10:15:29