Analiza i projektiranje diferencijske nabojske pumpe za fazno spregnutu petlju izvedenu u 130 nm SiGe CMOS tehnologiji

master's thesis

• Title (english): Analysis and Design of a Differential Charge Pump for PLL applications in 130-nm SiGe CMOS technology
• Author: David Osmanović
• Mentor: Adrijan Barić (mentor)
• Committee member: Adrijan Barić (predsjednik povjerenstva)
• Committee member: Marko Koričić (član povjerenstva)
• Committee member: Vladimir Čeperić (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2021-09-24, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Electrical Engineering

Abstract

Mikroelektronika i integrirani sklopovi predstavljaju okosnicu moderne civilizacije. Sklopovi velike brzine rada presudni su u informacijskom društvu u kojem živimo. Fazno spregnute petlje su osnovni gradivi elementi u komunikacijskim sklopovima. Tema ovog diplomskog rada je projektiranje diferencijske nabojske pumpe za fazno spregnutu petlju u 130 nm SiGe CMOS tehnologiji. Sklop nabojske pumpe generira kontrolni napon za niskopropusni filter i za naponski kontrolirani oscilator. Izlazni napon ovisi o signalima koji dolaze iz fazno-frekvencijskog detektora. Cilj je projektirati nabojsku pumpu kod koje izlazni napon ostaje korektan za široki raspon napona napajanja, temperature i tehnoloških parametara. Potvrditi da se nabojska pumpa ponaša u skladu sa specifikacijama kroz rezultate DC, tranzijentnih i Monte Carlo simulacija. Rezultate prikazati u grafičkom i tabličnom obliku. Objasniti princip rada sklopa i odabir dimenzija tranzistora. Predložiti moguća poboljšanja sklopa.

Abstract (english)

Microelectronics and integrated circuits represent the backbone of modern civilization. High-speed circuits are crucial in the information society in which we live and phase-locked loops are the basic building blocks of communication circuits. The topic of this thesis is the design of a differential charge pump for a phase-locked loop in 130 nm SiGe CMOS technology. The circuit generates control voltage for the low-pass filter and the voltage-controlled oscillator. The output voltage is dependent on the input signals from the phase frequency detector. The goal is to design a charge pump whose voltage output remains correct throughout a wide range of supply voltages, temperatures, and technology parameters. To confirm that the charge pump complies with the specifications, the results of DC, transient, and Monte Carlo simulations have to be represented in a graphical and tabular form. The circuit functionality and the choice of transistor dimensions have to be explained. Further improvements of the circuit have to be proposed.

• Keywords: nabojska pumpa; fazno spregnuta petlja; integrirano sklopovlje
• Keywords (english): charge pump; phase locked loop; integrated circuit
• Language: english
• URN:NBN: urn:nbn:hr:168:213277
• Study programme: Title: Electrical Engineering and Information Technology; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije (magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2023-01-13 13:22:44