Modeliranje i razvoj sklopovskih sustava u UML i VHDL okruženju

scientific master's theses

• Author: Josip Matanović
• Mentor: Slobodan Ribarić (mentor)
• Committee member: Leo Budin (predsjednik povjerenstva)
• Committee member: Slobodan Ribarić (član povjerenstva)
• Committee member: Karolj Skala (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; (Department of Electronics, Microelectronics, Computer and Intelligent Systems); Zagreb
• Defense date and country: 2004, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Electrical Engineering
• Universal decimal classification (UDC): 621.3 - Electrical engineering

Abstract

Jezik UML (Unified Modeling Language) je grafički jezik za vizualizaciju, specifikaciju, konstrukciju i dokumentiranje prvenstveno složenih programskih sustava. Jezik UML predstavlja standardan način predočavanja sustava i to od razine zamisli pa sve do konkretnih komponenti kao što su klase namijenjene specifičnom programskom jeziku, baze podataka i ponovno iskoristive programske komponente. UML nije jezik za (vizualno) programiranje ali se model predočen u UML jeziku može preslikati u ciljni programski jezik. Zadatak magistarskog rada je istražiti i razviti metode koje se temelje na modeliranju UML jezikom, ali za složene sklopovske strukture i sustave, s tim da je preslikavanjem iz UML modela, novi model predočen sklopovskim jezikom VHDL. Na taj će se način integrirati okruženje UML jezika s razvojnim okruženjem VHDL jezika, odnosno moći će se uporabiti modeli u UML notaciji za automatsko generiranje VHDL koda. Ovako opisani pristup primijenit će se u oblikovanju procesora arhitekture RISC.

Abstract (english)

The Unified Modeling Language (UML) is a graphical language for visualizing, specifying, constructing, and documenting the artifacts of a software-intensive system. The UML gives a standard way to write a system's blueprints, covering conceptual things as well as concrete things, such as classes written in a specific programming language, database schemas, and reusable software components. The UML is not a visual programming language, but its models can be directly connected to a target programming language. Major goal of this work is to investigate and to develop methods, based on UML modelling, for complex hardware structure and systems, so mapping UML model, a new model will be represented in hardware description language VHDL. In that way UML environment will be integrated with development environment of VHDL, in other words models in UML notation can be used for automatic VHDL code generation. This new approach will be presented through modelling of a processor based on RISC.

• Keywords: UML; VHDL; modeliranje; razvoj sklopovskih sustava
• Keywords (english): UML; VHDL; modelling; hardware system developing
• Language: croatian
• URN:NBN: urn:nbn:hr:168:560822
• Study programme: Title: Postgraduate master programme in electrical engineering; Study programme type: university; Study level: postgraduate; Academic / professional title: Magistar znanosti elektrotehnike (Magistar znanosti elektrotehnike)
• Type of resource: Text
• Extent: 112 str. ; 30 cm
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2020-03-02 13:47:04