Dizajn i FPGA implementacija decimacijskog filtra temeljenog na izoštravanju i kompenzaciji amplitude

master's thesis

• Title (english): Design and FPGA Implementation of Decimation Filter Based on Amplitude Sharpening and Compensation
• Author: Duje Mušura
• Mentor: Ana Sović Kržić (mentor)
• Committee member: Ana Sović Kržić (predsjednik povjerenstva)
• Committee member: Mladen Vučić (član povjerenstva)
• Committee member: Goran Molnar (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2019-07-10, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Electrical Engineering

Abstract

Proučeni su postupci dizajna i realizacije rekurzivnih FIR decimatora temeljenih na polinomnom izoštravanju i kompenzaciji amplitude. Razvijeni su postupci određivanja optimalnih koeficijenata polinoma koji su izraženi kao sume potencija broja 2 te osiguravaju minmax izoštravanje u područjima preklapanja spektra. Nadalje, za kompenzator je razvijen postupak određivanja optimalnih koeficijenata koji su također izraženi kao sume potencija broja 2, a pritom osiguravaju minimalno odstupanje amplitude u danom području propuštanja. Cjelokupni dizajn decimacijskog filtra napravljen je u Matlab-u. Za dobivene koeficijente te za postojeći fizički ostvariv model izoštrenog CIC filtra razvijen je model decimacijskog filtra bez upotrebe množila pisan u jeziku VHDL. Konačno, model je uhodan na sustavu ZedBoard.

Abstract (english)

The procedures for design and realization of recursive FIR decimators based on polynomial sharpening and amplitude compensation have been studied. Procedures for determining the optimal coefficients of polynomials, expressed as sums of power of 2, have been developed providing minmax sharpening in folding bands area. Furthermore, for the compensator, a procedure for determining optimal coefficients which are also expressed as sums of power of 2 was developed, ensuring a minimum deviation of the amplitude in the given passband area. The entire decimation filter design was made using Matlab. For the obtained coefficients and for the existing physically achievable model of the sharpened CIC filter, a multiplier-free model was developed in VHDL. Finally, the model has been launched on the ZedBoard system.

• Keywords: FPGA; CIC filtar; decimacijski filtar; izoštravanje polinomom; kompenzacija amplitude; Zedboard
• Keywords (english): FPGA; CIC filter; decimation filter; polynomial sharpening; amplitude compensation; Zedboard
• Language: croatian
• URN:NBN: urn:nbn:hr:168:527350
• Study programme: Title: Electrical Engineering and Information Technology; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije (magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2020-01-07 20:42:10