Dizajn i FPGA implementacija nerekurzivnog poboljšanog CIC filtra bez množila

master's thesis

• Title (english): Design and Multiplierless FPGA Implementation of Non-Recursive Improved CIC Filter
• Author: Marija Knežević
• Mentor: Davor Petrinović (mentor)
• Committee member: Davor Petrinović (predsjednik povjerenstva)
• Committee member: Mladen Vučić (član povjerenstva)
• Committee member: Goran Molnar (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2019-07-11, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Electrical Engineering

Abstract

U radu su proučeni postupci dizajna i realizacije filtara s konačnim impulsnim odzivom (FIR) koji proizlaze iz različitih tehnika poboljšanja amplitudne karakteristike CIC filtra. Posebno su proučeni postupci koji rezultiraju prijenosnim funkcijama niskog reda i imaju cjelobrojne koeficijente. Takve prijenosne funkcije mogu se učinkovito realizirati nerekurzivnim strukturama koje ne sadrže množila. Svaki cjelobrojni koeficijent zapisan je kao suma potencija broja dva, a zatim je iz sume pronađena optimalna realizacija odnosno ona koja sadrži najmanji broj zbrajala. Optimalna realizacija za svaki pojedini koeficijent pronađena je primjenom iscrpnog pretraživanja nad skupom direktnih acikličkih grafova. Razvijen je fizički ostvariv model filtra koji ima direktnu realizaciju. Model je razvijen u jeziku VHDL te optimiziran za implementaciju na programabilnim logičkim poljima (FPGA). Razvijeno je odgovarajuće ispitno okruženje, provedena simulacija te je model uhodan na stvarnom sklopovlju.

Abstract (english)

In the thesis, the design and implementation of the finite impluse response filters (FIRs) based on amplitude improvements of the CIC filters, was studied. Particulary were considered techniques that result in low-order transfer functions and have integer coefficients. Such transfer functions can be efficiently realized with non-recusrive structures that do not employ general purpose multipliers. Each integer coefficient was represented as sum of power of two. Optimal coefficient realization, with lowest number of adders, was obtained by applying exhaustive search over the set of directed acyclic graphs (DAGs). Register transfer level (RTL) model has been developed in VHDL langugage and optimized for development in programmable logic fields (FPGAs). An appropriate test environment was developed, simuation was carried out, and the model was implemented on real hardware.

• Keywords: CIC filtar; FIR filtar; cjelobrojni koeficijenti; direktni aciklički grafovi; realizacija bez množila; VHLD; FPGA
• Keywords (english): CIC filter; FIR filter; integer coefficients; directed acyclic graphs; multiplierless realization; VHDL; FPGA
• Language: croatian
• URN:NBN: urn:nbn:hr:168:062764
• Study programme: Title: Electrical Engineering and Information Technology; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije (magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2020-01-07 19:09:35