No public access
master's thesis
FPGA implementation of variable delay filters based on Farrow structure

Antonio Benc (2016)
University of Zagreb
Faculty of Electrical Engineering and Computing
Cite this document...

Benc, A. (2016). FPGA implementacija filtara s varijabilnim kašnjenjem temeljena na Farrow strukturi (Master's thesis). Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:710701

Benc, Antonio. "FPGA implementacija filtara s varijabilnim kašnjenjem temeljena na Farrow strukturi." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2016. https://urn.nsk.hr/urn:nbn:hr:168:710701

Benc, Antonio. "FPGA implementacija filtara s varijabilnim kašnjenjem temeljena na Farrow strukturi." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2016. https://urn.nsk.hr/urn:nbn:hr:168:710701

Benc, A. (2016). 'FPGA implementacija filtara s varijabilnim kašnjenjem temeljena na Farrow strukturi', Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 23 April 2019, https://urn.nsk.hr/urn:nbn:hr:168:710701

Benc A. FPGA implementacija filtara s varijabilnim kašnjenjem temeljena na Farrow strukturi [Master's thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2016 [cited 2019 April 23] Available at: https://urn.nsk.hr/urn:nbn:hr:168:710701

A. Benc, "FPGA implementacija filtara s varijabilnim kašnjenjem temeljena na Farrow strukturi", Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2016. Available at: https://urn.nsk.hr/urn:nbn:hr:168:710701