prikaz prve stranice dokumenta Prevođenje tokovnog programa za heterogenu ugradbenu platformu s procesorom RISC-V
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undergraduate thesis
Prevođenje tokovnog programa za heterogenu ugradbenu platformu s procesorom RISC-V
2018. urn:nbn:hr:168:360217
Šeler, Martin
University of Zagreb
Faculty of Electrical Engineering and Computing

Cite this document

Šeler, M. (2018). Prevođenje tokovnog programa za heterogenu ugradbenu platformu s procesorom RISC-V (Undergraduate thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:360217

Šeler, Martin. "Prevođenje tokovnog programa za heterogenu ugradbenu platformu s procesorom RISC-V." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2018. https://urn.nsk.hr/urn:nbn:hr:168:360217

Šeler, Martin. "Prevođenje tokovnog programa za heterogenu ugradbenu platformu s procesorom RISC-V." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2018. https://urn.nsk.hr/urn:nbn:hr:168:360217

Šeler, M. (2018). 'Prevođenje tokovnog programa za heterogenu ugradbenu platformu s procesorom RISC-V', Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 24 April 2024, https://urn.nsk.hr/urn:nbn:hr:168:360217

Šeler M. Prevođenje tokovnog programa za heterogenu ugradbenu platformu s procesorom RISC-V [Undergraduate thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2018 [cited 2024 April 24] Available at: https://urn.nsk.hr/urn:nbn:hr:168:360217

M. Šeler, "Prevođenje tokovnog programa za heterogenu ugradbenu platformu s procesorom RISC-V", Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2018. Available at: https://urn.nsk.hr/urn:nbn:hr:168:360217

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Metadata
TitlePrevođenje tokovnog programa za heterogenu ugradbenu platformu s procesorom RISC-V
Title (english)Stream Program Compilation for Heterogeneous Embedded Platform with RISC-V Processor
AuthorMartin Šeler
MentorJosip Knezović (mentor)
Committee memberJosip Knezović (predsjednik povjerenstva)
Committee memberHrvoje Mlinarić (član povjerenstva)
Committee memberBranimir Pervan (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2018-07-13, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Abstract
Ovaj rad istražuje funkcionalnost i potencijal tokovnog programa na RISC-V procesoru. Testiranje je provedeno na ugradbenoj verziji RISC-V arhitekture na kojoj je Linux s SMP podrškom kako bi se evaluiralo ubrzanje dobiveno paralelizacijom koju provodi optimizirajući tokovni prevoditelj.
Abstract (english)
This thesis explores the functionality and potential for stream computing on RISC-V processors. Testing is done on the embedded version of RISC-V running a Linux for SMP support in order to evaluate speedup gained by parallelisation made by optimising stream compiler.
Keywords
Keywords (english)
Languageenglish
URN:NBNurn:nbn:hr:168:360217
Study programmeTitle: Computing
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
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Created on2019-03-14 01:12:09