University of Zagreb Faculty of Electrical Engineering and Computing
Cite this document
Strižić, L. (2018). Izvedba ubrzivača za duboko učenje u heterogenom sustavu s procesorom RISC-V i tehnologijom FPGA (Master's thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:136621
Strižić, Luka. "Izvedba ubrzivača za duboko učenje u heterogenom sustavu s procesorom RISC-V i tehnologijom FPGA." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2018. https://urn.nsk.hr/urn:nbn:hr:168:136621
Strižić, Luka. "Izvedba ubrzivača za duboko učenje u heterogenom sustavu s procesorom RISC-V i tehnologijom FPGA." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2018. https://urn.nsk.hr/urn:nbn:hr:168:136621
Strižić, L. (2018). 'Izvedba ubrzivača za duboko učenje u heterogenom sustavu s procesorom RISC-V i tehnologijom FPGA', Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 20 August 2024, https://urn.nsk.hr/urn:nbn:hr:168:136621
Strižić L. Izvedba ubrzivača za duboko učenje u heterogenom sustavu s procesorom RISC-V i tehnologijom FPGA [Master's thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2018 [cited 2024 August 20] Available at: https://urn.nsk.hr/urn:nbn:hr:168:136621
L. Strižić, "Izvedba ubrzivača za duboko učenje u heterogenom sustavu s procesorom RISC-V i tehnologijom FPGA", Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2018. Available at: https://urn.nsk.hr/urn:nbn:hr:168:136621