Izvedba ubrzivača za duboko učenje u heterogenom sustavu s procesorom RISC-V i tehnologijom FPGA

master's thesis

• Title (english): Deep Learning Accelerator for FPGA-Based Heterogeneous System with RISC-V Processor
• Author: Luka Strižić
• Mentor: Josip Knezović (mentor)
• Committee member: Josip Knezović (predsjednik povjerenstva)
• Committee member: Hrvoje Mlinarić (član povjerenstva)
• Committee member: Daniel Hofman (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2018-09-18, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing

Abstract

Ovaj diplomski rad istražuje binariziranu implementaciju neuronske mreže na heterogenom računalnom sustavu koji je zasnovan na RISC-V instrukcijskom setu, zvanom PULPissimo, koristeći akcelerator množenja i zbrajanja, te uspoređuje njene performanse s dvije obične neuronske mreže, od kojih jedna koristi akcelerator, a druga ne. Mreže su učene na računalu viših performansi, te je samo unaprijedni prolaz implementiran na PULPissimu, kako bi se zadovoljio češći način korištenja neuronskih mreža. Unaprijedni prolaz nije imao koristi od akceleracije zbog dodatnih troškova postavljanja posla, sporog pristupa memoriji, neoptimirane implementacije i malene mreže, iako, binarizirano računanje je pokazalo očekivano poboljšanje performansi i korištenja memorije.

Abstract (english)

This master thesis explores a binarized neural network implementation on a heterogenous, RISC-V based microcontroller, called PULPissimo, with the help of a multiply-and-accumulate accelerator, and compares its performance to two regular, non-binarized neural network implementations, one using the accelerator and the other not. Networks were trained on a more powerful computer and only the forward pass was implemented in PULPissimo to suit a common neural network use pattern. The forward pass did not benefit from using the accelerator, due to its setup overhead, memory access bottlenecks, a low-effort implementation, and the small network, however, the binarized computation did show expected performance and memory consumption improvements.

• Keywords: duboko učenje; RISC-V; višeslojni perceptron; MLP; binarizirana; neuronska mreža; FPGA; PULP; PULPissimo
• Keywords (english): deep learning; RISC-V; multilayer perceptron; MLP; binarized; neural networks; FPGA; PULP; PULPissimo
• Language: english
• URN:NBN: urn:nbn:hr:168:136621
• Study programme: Title: Computing; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2019-03-14 01:00:28