Dizajn i implementacija FIR filtara s rijetkim impulsnim odzivima

master's thesis

• Title (english): Design and Implementation of Sparse FIR Filters
• Author: Anita Frljić
• Mentor: Mladen Vučić (mentor)
• Committee member: Mladen Vučić (predsjednik povjerenstva)
• Committee member: Damir Seršić (član povjerenstva)
• Committee member: Goran Molnar (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2017-07-12, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Electrical Engineering

Abstract

U radu su opisani dizajn i implementacija FIR filtara s rijetkim impulsnim odzivima. Za dobivanje rijetkih koeficijenata filtra (K) koristi se algoritam iterativne promjene praga (IHT). Aproksimacija je dobivena metodom najmanjih kvadrata u kombinaciji s algoritmom padajućeg gradijenta. Parametar K predstavlja broj koeficijenata filtra koji su različiti od nule i koristi se umjesto originalnog reda filtra, čime se ostvaruje implementacija većih redova filtra na sklopovlje uz isto zauzeće memorije. U memoriju se spremaju redom dobiveni K koeficijenti pri čemu se pojedinom uzorku, koji se množi s koeficijentima tijekom konvolucije, daje odmak pozicijom koeficijenta. Razvijen je fizički ostvariv model FIR filtra s rijetkim impulsnim odzivom korištenjem jednog množila i akumulatora i optimiran je za implementaciju na programabilnim logičkim poljima (FPGA). Implementacija na Zynq sklopovlju pokazuje da se rijetkom reprezentacijom koeficijenata, koristeći navedeni algoritam, mogu ostvariti dobra svojstva filtra.

Abstract (english)

In this thesis the design and implementation of sparse FIR filters have been described. The iterative hard thresholding algorithm (IHT) is used for acquiring the coefficients (K), and least squares method with gradient descent algorithm for aproximation. The K parameter represents the number of non-zero coefficients and it is used instead of the original filter order, what enables the implementation of higher order filters with the same memory requirements. Calculated K coefficients are saved in the memory, while each sample, multiplied with the coefficients during the convolution, gains an offset depending on the coefficient position. Physically implementable sparse FIR filter with the usage of a single multiplier and accumulator was developed and optimised for implementation on FPGA. Implementation on Zynq evaluation platform demonstrates that filter with good characteristics is possible with sparse coefficients.

• Keywords: filtar s konačnim impulsnim odzivom; rijetkost; algoritam iterativne promjene praga; algoritam padajućeg gradijenta; metoda najmanjih kvadrata; VHDL; Xilinx; Zynq; Xillybus
• Keywords (english): finite impulse response filter; sparsity; Iterative Hard Thresholding Algorithm; Gradient Descent Algorithm; Least Squares Method; VHDL; Xilinx; Zynq; Xillybus
• Language: croatian
• URN:NBN: urn:nbn:hr:168:280665
• Study programme: Title: Electrical Engineering and Information Technology; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije (magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2019-03-13 20:18:52