Izvedba aritmetičkih naredaba SIMD na procesoru FRISC

undergraduate thesis

• Title (english): Arithmetic SIMD Instructions Implementation in FRISC Processor
• Author: Tomislav Milković
• Mentor: Mario Kovač (mentor)
• Committee member: Mario Kovač (predsjednik povjerenstva)
• Committee member: Daniel Hofman (član povjerenstva)
• Committee member: Alen Duspara (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2017-07-10, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing

Abstract

Cilj ovog završnog rada bio je izvesti skup naredbi za vektorsku obradu podataka (single instruction, multiple data – SIMD) na procesoru FRISC. Trebalo je nadograditi FRISC-ovu arhitekturu novim registrima veće širine te dodati novu aritmetičko-logičku jedinicu koja će moći obrađivati nekoliko podataka odjednom. Dodano je 16 64-bitnih registara te 8 128-bitnih registara. Nova SIMD ALU može raditi s podacima širine 8, 16, 32 ili 64 bita.

Također je prilagođena upravljačka jedinica kako bi na temelju novih naredbi mogla postavljati upravljačke signale za skup registara i SIMD ALU.

Za izradu projekta korištena je pločica Xilinx PYNQ-Z1 temeljena na Artix-7 seriji FPGA. VHDL kod pisan je u razvojnom okruženju Xilinx Vivado WebPack. Izrađena je i simulacija modula dodanih u arhitekturu FRISC procesora te je čitav sustav ispitan i na PYNQ-Z1 pločici.

Abstract (english)

The goal of this bachelor’s thesis was to implement instruction set for vector processing of data (single instruction, multiple data) in FRISC processor. FRISC processor’s architecture was updated with registers of larger widths and with new arithmetic logic unit which could operate on more data in parallel. 16 new 64-bit registers were added to the register set, along with 8 128-bit registers. The new SIMD ALU can operate on 8-bit, 16-bit, 32-bit and 64-bit data.

The control unit was also updated, so it would set the control signals for register set and SIMD ALU according to newly added instructions.

For development of this project, a Xilinx PYNQ-Z1 board was used, which is based on Artix-7 series FPGA. VHDL code was written in Xilinx Vivado WebPack design suite. Also, a simulation of newly added modules to the FRISC architecture was carried out, along with testing of the whole system on PYNQ-Z1 board.

• Keywords: single instruction-multiple data; SIMD; proširenje; procesorska arhitektura; FRISC; Xilinx; PYNQ-Z1; Vivado; arhitektura računala
• Keywords (english): single instruction-multiple data; SIMD; extension; processor architecture; FRISC; Xilinx; PYNQ-Z1; Vivado; computer architecture
• Language: croatian
• URN:NBN: urn:nbn:hr:168:160319
• Study programme: Title: Computing; Study programme type: university; Study level: undergraduate; Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2019-03-13 19:04:46