Implementacija neuronske mreže na FPGA sklopovima

undergraduate thesis

• Title (english): Implementation of neural network on FPGA devices
• Author: Jurica Rešetar
• Mentor: Mladen Vučić (mentor)
• Committee member: Mladen Vučić (predsjednik povjerenstva)
• Committee member: Ana Sović Kržić (član povjerenstva)
• Committee member: Maja Jurišić Bellotti (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2016-09-07, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing

Abstract

Cilj ovog rada bio je izraditi model umjetne neuronske mreže, pogodan za ostvarivanje u FPGA sklopovima, te dodatno sklopovsko ubrzanje dobivanja rezultata prijenosnih funkcije neurona. Za dobivanje zadovoljavajućeg modela korišteni su alati Matlab i programski jezik C. Model je napravljen, istreniran i evaluiran u alatu Matlab. Korišten je alat Matlab zbog jednostavnosti korištenja već dostupnih biblioteka za rad s umjetnim neuronskim mrežama. Na temelju Matlab modela, stvoren je C model. Izradom potrebne okoline oko razvijenog C modela, ostvaren je sustav koji na zadatku klasifikacije prometnih znakova postiže vrlo visoku točnost klasifikacije od 96.6% što ga čini vrlo dobrim sustavom u području klasifikacije slika. Dodatno, ostvareno je i sklopovsko rješenje s ciljem ubrzanja računanja rezultata prijenosnih funkcija svakog sloja razvijene neuronske mreže. Za taj cilj, dvije funkcije koje predstavljaju prijenose funkcije skrivenog sloja i izlaznog sloja mreže, ostvarene su u sklopovlju korištenjem IP jezgri. Na kraju, razvijen je cjelokupni sustav koji objedinjuje sklopovski i programski pristup. Koristeći Vivado alat i Xilinx SDK program stvoren je sklopovski sustav s razvijenim IP jezgrama i procesorom za koji je razvijena aplikacija. Aplikacija obavlja identičan zadatak kao i C aplikacija no za računanje izlaza neurona koristi razvijene IP jezgre što dovodi do znatnog ubrzanja cijelog sustava što je i bio cilj ovog rada.

Abstract (english)

The aim of this study was to develop an artificial neural network suitable for implementation in FPGA device. Additionally, hardware solution for transfer function calculation acceleration was considered and developed. For getting an appropriate model of an artificial neural network Matlab tool as C programming language are used. Matlab is used to develop, train and evaluate an artificial neural network model since it's equipped with neural network toolbox. Based on the Matlab model a C model is made. Using it, the whole system for traffic signs classification is developed. The system is state-of-the-are since its classification accuracy is about 96.6% on selected dataset. Additionally, hardware acceleration solution is developed using IP cores and FPGA device. Transfer functions for both layers are developed as IP cores using Vivado HLS tool. The whole system for image classification using software and hardware approach is developed as final step in the study. It's made with help of the Vivado and Xilinx SDK tools. The system except hardware has also software part which is a bare-metal application. Its purpose is to implement the same algorithm as one developed in C but using IP cores for transfer functions calculations. By doing so the whole classification task is accelerated considerably.

• Keywords: umjetne neuronske mreže; klasifikacija slika; programabilna logička polja; FPGA; IP jezgre; sklopovsko ubrzanje
• Keywords (english): artificial neural networks; image classification; Field Programmable Gate Arrays; FPGA; IP cores; hardware acceleration
• Language: croatian
• URN:NBN: urn:nbn:hr:168:914259
• Study programme: Title: Computing; Study programme type: university; Study level: undergraduate; Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2018-02-06 11:35:10