FPGA implementacija DCT konverzije i dekvantizacije JPEG dekodera

undergraduate thesis

• Title (english): FPGA implementation of DCT conversion and dequantization of JPEG decoder
• Author: Borna Krušlin
• Mentor: Daniel Hofman (mentor)
• Committee member: Daniel Hofman (član povjerenstva)
• Committee member: Luka Mrković (član povjerenstva)
• Committee member: Stipe Mišković (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2024-09-11, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing

Abstract

Rad se bavi analizom procesa dekodiranja slika kodiranih JPEG standardom. Cilj je identificirati uska grla algoritma dekodiranja slike te ih hardverski izvesti na Zynq SoC platformi kako bi se ubrzao proces dekodiranja. Fokus rada je na implementaciji, sintezi i analizi koraka dekvantizacije i IDCT transformacije obradbenih blokova slike. Programska podloga ovog rada je Jaguar JPEG biblioteka iz koje je izolirana cjelobrojna implementacija IDCT transformacija. Kao sintetizator korišten je alat Xilinx Vitis HLS koji sintetizira C/C++ kod u RTL opis hardvera u jezicima Verilog i VHDL u kombinaciji s programom Xilinx Vivado koji se koristi za implementaciju sustava na SoC. Analiza dobivene arhitekture izvedena je na ARM procesoru koji je integriran u Zynq SoC platformu
za čije je programiranje korištena Pynq biblioteka u programskom jeziku Python.

Abstract (english)

This work is focused on the analysis of image decoding using a JPEG library. The goal of this work is to identify the bottlenecks in the image decoding process and to create hardware implementations of these stages in order to accelerate the process of image decompression. This work is focused on implementation, synthesis and analysis of the dequantization and IDCT (Inverse Discrete Cosine Transform) stages of JPEG decoding. The software basis for this work is the Jaguar JPEG library, from which the integer implementation of IDCT transformation has been isolated. Synthesis was done using the Xilinx Vitis HLS (High-Level Synthesis) tool which synthesizes C/C++ code into RTL hardware description in Verilog and VHDL. The Xilinx Vivado was used to implement the hardware on the SoC. The analysis of the obtained architecture was performed on the ARM processor integrated into the Zynq SoC platform, for which the Python Pynq framework was used for programming.

• Keywords: FPGA; Digitalni dizajn; HLS; JPEG dekodiranje; IDCT; dekvantizacija; Vitis HLS; Vivado; C++; Zynq
• Keywords (english): FPGA; Digital design; HLS; JPEG decoding; IDCT; dequantization; Vitis HLS; Vivado; C++; Zynq
• Language: croatian
• URN:NBN: urn:nbn:hr:168:952997
• Study programme: Title: Computing; Study programme type: university; Study level: undergraduate; Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2024-10-12 21:14:51