Model i izvedba 32-bitnog procesora RISC-V s podrškom za prekide

master's thesis

• Title (english): Model and implementation of 32-bit RISC-V processor with support for interrupts
• Author: Matej Grzunov
• Mentor: Tomislav Hrkać (mentor)
• Committee member: Tomislav Hrkać (predsjednik povjerenstva)
• Committee member: Stjepan Groš (član povjerenstva)
• Committee member: Nikolina Frid (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2024-07-02, Croatia

Abstract

Prekidi toka izvođenja temelj su izrade efikasne i robusne programske podrške za
ugradbene računalne sustave, jer smanjuju udio radnog čekanja u programima te
omogućavaju odgovor na očekivane događaje i neočekivane greške tijekom rada
procesora. U ovom diplomskom radu razvijen je RISC-V procesor s podrškom za prekide
toka izvođenja i RISC-V naprednu prekidnu arhitekturu. Izvedeni procesor sadrži jednu
procesorsku jezgru s klasičnom RISC protočnom strukturom s 5 protočnih razina,
rudimentarnu memoriju, te ulazno/izlazne jedinice za komunikaciju s vanjskim svijetom.
Procesor je opisan SystemVerilog jezikom, sintetiziran i izveden za FPGA čip, te
programiran i upogonjen na ULX3S razvojnoj pločici.

Abstract (english)

Execution flow interrupts are the basis of efficient and robust embedded systems’ software
because they reduce the share of the time spent in a program loop waiting for input/output
operations to finish. They also enable a processor to respond to expected events and
unexpected errors during runtime. As part of this thesis, a RISC-V processor that supports
execution flow interrupts was developed, implementing the RISC-V advanced interrupt
architecture. Its single processor core includes the classic RISC 5-stage pipeline. The
developed processor also includes a rudimentary memory implementation, and
input/output units it can use to communicate with the outside world. The processor was
described using SystemVerilog, synthesized, and implemented for an FPGA chip. After
programming it was run on the ULX3S development board.

• Keywords: RISC-V; RV32I; RISC-V AIA; arhitektura skupa naredbi (ISA); arhitektura računala; prekid; iznimka; protočna struktura; FPGA; ULX3S; ugradbeni računalni sustav
• Keywords (english): RISC-V; RV32I; RISC-V AIA; instruction set architecture (ISA); computer architecture; interrupt; exception; instruction pipeline; FPGA; ULX3S; embedded system
• Language: croatian
• URN:NBN: urn:nbn:hr:168:458292
• Study programme: Title: Computing; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2024-10-12 20:45:00