Sustav RISC-V na pločici FPGA

master's thesis

• Title (english): RISC-V system on an FPGA board
• Author: Luka Dautović
• Mentor: Daniel Hofman (mentor)
• Committee member: Daniel Hofman (član povjerenstva)
• Committee member: Hrvoje Mlinarić (član povjerenstva)
• Committee member: Josip Knezović (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2024-07-02, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing

Abstract

Ovaj rad proučava arhitekturu RISC-V instrukcijskog skupa RV32I i njegovih standardnih proširenja. Koristeći razumijevanje arhitekture RISC-V instrukcijskih skupova rad nudi pregled dostupnih jezgri otvorenog koda te razmatra mogućnosti implementacije jezgre prikladne za PYNQ-Z1 uređaj, koji koristi Jupyter platformu za interaktivno računarstvo. Konačno, rad iznosi detalje implementacije jezgre PicoRV32 na navedenom uređaju, opisuje postupak rješavanja implementacijskih poteškoća te demonstracijsko ispitivanje instrukcija RV32IMC instrukcijskog skupa implementiranog u PicoRV32 procesorskoj jezgri.

Abstract (english)

This paper studies the RISC-V instruction set architecture RV32I and its standard extensions. Utilizing an understanding of the RISC-V instruction set architectures, the paper provides an overview of available open-source cores and considers the possibilities of implementing a core suitable for the PYNQ-Z1 device, which uses the Jupyter platform for interactive computing. Finally, the paper presents the details of implementing the PicoRV32 core on the aforementioned device, describes the process of resolving implementation difficulties, and demonstrates a test of the RV32IMC instruction set implemented in the PicoRV32 processor core.

• Keywords: RISC-V arhitektura instrukcijskog skupa; RV32IMC; RV64IMC; PYNQ-Z1 razvojna FPGA pločica; PYNQ platforma; Jupyter platforma za interaktivno računarstvno; Jupyter Notebooks; PicoRV32 minimalistička RISC-V jezgra; Rocket Core; SweRV; BOOM (Berkeley Out-of-Order Machine); Vexriscv; Otvoreno računarstvo
• Keywords (english): RISC-V instruction set architecture; RV32IMC; RV64IMC; PYNQ-Z1 development FPGA board; PYNQ platform; Jupyter platform for interactive computing; Jupyter Notebooks; PicoRV32 minimalist RISC-V core; Rocket Core; SweRV; BOOM (Berkeley Out-of-Order Machine); Vexriscv; Open computing
• Language: croatian
• URN:NBN: urn:nbn:hr:168:845579
• Study programme: Title: Computing; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2024-10-12 20:24:50