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undergraduate thesis
Izvedba aritmetičko-logičke jedinice za FRISC-V procesor
2022. urn:nbn:hr:168:540361
Strunje, Duje
University of Zagreb
Faculty of Electrical Engineering and Computing

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Strunje, D. (2022). Izvedba aritmetičko-logičke jedinice za FRISC-V procesor (Undergraduate thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:540361

Strunje, Duje. "Izvedba aritmetičko-logičke jedinice za FRISC-V procesor." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2022. https://urn.nsk.hr/urn:nbn:hr:168:540361

Strunje, Duje. "Izvedba aritmetičko-logičke jedinice za FRISC-V procesor." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2022. https://urn.nsk.hr/urn:nbn:hr:168:540361

Strunje, D. (2022). 'Izvedba aritmetičko-logičke jedinice za FRISC-V procesor', Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 23 April 2024, https://urn.nsk.hr/urn:nbn:hr:168:540361

Strunje D. Izvedba aritmetičko-logičke jedinice za FRISC-V procesor [Undergraduate thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2022 [cited 2024 April 23] Available at: https://urn.nsk.hr/urn:nbn:hr:168:540361

D. Strunje, "Izvedba aritmetičko-logičke jedinice za FRISC-V procesor", Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2022. Available at: https://urn.nsk.hr/urn:nbn:hr:168:540361

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Metadata
TitleIzvedba aritmetičko-logičke jedinice za FRISC-V procesor
Title (english)Implementation of arithmetic logic unit for FRISC-V processor
AuthorDuje Strunje
MentorMario Kovač (mentor)
Committee memberMario Kovač (član povjerenstva)
Committee memberJosip Knezović (član povjerenstva)
Committee memberDaniel Hofman (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2022-09-02, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Abstract
U sklopu ovog završnog rada izvedena je i provjerena aritmeticko-logička jedinica za fakultetski RISC-V procesor. Rad svake naredbe je objašnjen i opisana su ubrzanja za svaku naredbu. Sklop je provjeren u simulaciji i potom izveden na ugradbenom računalnom sustavu Xilinx Zynq Pynq Z1. Kasnije je integriran u protočnoj strukturi samog procesora te su oni zajedno izvedeni i provjereni na istom ugradbenom računalnom sustavu. FRISC-V je 32-bitni jednojezgreni procesor s protocnom strukturom u pet faza kojemu je osnova RV32I.
Abstract (english)
In this thesis an arithmetic-logic unit was implemented and verified for faculty’s processor based on RISC-V ISA. Every operation was explained and optimised. The design was verified and then implemented on System on Chip Xilinx Zynq Pynq Z1. It was later integrated with processor. They were then both implemented and verified on the same SoC. FRISC-V is a 32-bit, single-core processor with a 5-stage pipeline based on RV32I.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:540361
Study programmeTitle: Computing
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
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Created on2023-01-15 11:16:20