Izvedba sučelja FRISC-V procesora prema mreži na čipu

undergraduate thesis

• Title (english): Implementation of FRISC-V network on chip interface
• Author: Luka Hanžek
• Mentor: Mario Kovač (mentor)
• Committee member: Mario Kovač (član povjerenstva)
• Committee member: Josip Knezović (član povjerenstva)
• Committee member: Daniel Hofman (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2022-07-01, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing

Abstract

U ovom radu predstavljena je i ispitana izvedba sučelja prema memoriji za RISC-V jezgru koje omogućava istovremeno povezivanje procesora s vanjskim sklopovljem i povezivanje memorije s podatkovnom i instrukcijskom sabirnicom procesora. Dana je ideja nadogradnje trenutnog rješenja za spajanje prema mreži na čipu. Opisan je postupak izrade rješenja. Rješenje je izvedeno i testirano pomoću Xilinx alata i Verilog\System Verilog jezika za opis sklopovlja.

Abstract (english)

This thesis presents an implementaion and testing of RISC-V memory interface which enables simultaneous linkeage of memory with external hardware and linkeage of memory with processors instruction and data busses. An idea of further extending the solution to support connecting to system on a chip is presented. The solution is built and tested using Xilinx tools and Verilog\System Verilog hardware decsription language.

• Keywords: RISC-V; Verilog; RAM; sustav na čipu; NOC; AXI
• Keywords (english): RISC-V; Verilog; RAM; network on chip; NOC; AXI
• Language: croatian
• URN:NBN: urn:nbn:hr:168:915975
• Study programme: Title: Computing; Study programme type: university; Study level: undergraduate; Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2023-01-15 10:16:58