Sklopovska implementacija bilateralnog filtra

master's thesis

• Title (english): Hardware implementation of bilateral filter
• Author: Filip Čevapović
• Mentor: Mladen Vučić (mentor)
• Committee member: Mladen Vučić (predsjednik povjerenstva)
• Committee member: Davor Petrinović (član povjerenstva)
• Committee member: Damir Seršić (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2015-07-08, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Electrical Engineering

Abstract

Digitalna obrada signala s vremenom postaje sve složenija i postavlja sve veće zahtjeve na sklopovlje. Obrada video signala se posebno ističe budući da je potrebno obrađivati relativno veliku količinu podataka u točno određenim vremenskim intervalima. FPGA sklopovi su ovdje našli svoju primjenu zbog mogućnosti postizanja velikih brzina rada korištenjem paralelne odnosno protočne strukture. U ovom radu je na FPGA sklopu implementiran bilateralni filtar, koji se koristi za obradu video signala, odnosno slike, i to prvenstveno za uklanjanje šuma. Iako vrlo sličan Gaussovom filtru, bilateralni filtar ima tu prednost da, unatoč zamućenju slike, čuva oštrinu rubova. Razvijeni filtar ima paralelnu odnosno protočnu strukturu, što znači da na svaki rastući brid takta na izlazu generira novi piksel filtrirane slike. Filtar je implementiran na FPGA sklopovima familije Virtex 5 proizvođača Xilinx, Inc. Na ovim sklopovima postignuta je frekvencija rada od 50 MHz, koja omogućuje filtriranje video zapisa razlučivosti 1600x1200 piksela s osvježavanjem od 25 slika u sekundi.

Abstract (english)

Digital signal processing is becoming more complex and constantly requires better hardware performance. Video processing especially stands out since it means processing relatively large amounts of data in given periods of time. FPGA devices are widely used in this area because of their parallel and pipelined structure and consequently high-speed operation. This paper brings an FPGA implementation of bilateral filter, which is used for video and image processing, which primarily includes denoising. Although it’s very similar to Gaussian filter, bilateral filter has the advantage of preserving edges in the image, even though it blurs the rest of the image. Implemented filter has parallel and pipelined structure, which means it generates new pixel of the filtered image on every rising edge of the clock signal. Filter is implemented on Virtex 5 FPGA devices manufactured by Xilinx, Inc. Achieved frequency on this devices is 50 MHz, which allows refresh rate of 25 frames per second while filtering 1600x1200 video signal.

• Keywords: bilateralni filtar; programabilna logička polja; FPGA; sklopovska implementacija; digitalna obrada signala; obrada video signala; obrada slike
• Keywords (english): bilateral filter; programmable logic array; FPGA; hardware implementation; digital signal processing; video processing; image processing
• Language: croatian
• URN:NBN: urn:nbn:hr:168:017348
• Study programme: Title: Electrical Engineering and Information Technology; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije (magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2018-02-06 08:17:36