Izvedba sklopovskog akceleratora za procesor RISC-V

master's thesis

• Title (english): Implementation of hardware accelerator for RISC-V processor
• Author: Luka Macan
• Mentor: Mario Kovač (mentor)
• Committee member: Mario Kovač (predsjednik povjerenstva)
• Committee member: Josip Knezović (član povjerenstva)
• Committee member: Daniel Hofman (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2019-07-04, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing

Abstract

Tema ovog diplomskog rada je implementacija akceleratora za obradu slike za RISC-V procesor unutar heterogenog sustava.
HERO platforma je odabrana za istraživanje i razvoj, s obzirom na to da već implementira heterogeni sustav na čipu (engl. Heterogeneous System on Chip (HESoC)) i posjeduje programsku podršku za njegovo programiranje.
Za sklopovsko ubrzanje izabran je algoritam pretvorbe piksela iz RGB u Y'CbCr prostor boja.
Navedeni algoritam implementiran je kao sklopovski procesni ubrzivač (engl. Hardware Processing Engine (HWPE)).
Za integraciju s HERO platformom, iskorišteni su gotovi HWPE moduli.
Implementacija postiže ubrzanje od 24 puta u odnosu na programsku implementaciju na jednoj RISC-V jezgri te 3 puta u odnosu na paralelnu implementaciju za 8 RISC-V jezgri.

Abstract (english)

The topic of this theses was the implementation of an image processing accelerator for a RISC-V processing core in a heterogeneous system.
The HERO platform, which implements a heterogeneous system on chip and its software stack, was used for research and development of the accelerator.
The accelerated algorithm was the color conversion from RGB to Y'CbCr space.
It was implemented as a hardware processing engine.
Ready HWPE modules were used for integration with the HERO platform.
The implementation achieved a speedup of 24 times compared to the single core RISC-V software implementation and a speedup of 3 times compared to the 8 core RISC-V parallel implementation.

• Keywords: RISC-V; akcelerator; HERO; HESoC; obrada slike
• Keywords (english): RISC-V; accelerator; HERO; HESoC; image processing
• Language: english
• URN:NBN: urn:nbn:hr:168:359499
• Study programme: Title: Computing; Study programme type: university; Study level: graduate; Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2020-01-07 19:55:33