Analiza kodiranja videa visoke rezolucije na procesoru RISC-V

undergraduate thesis

• Title (english): High Resolution Video Encoding Analysis on the RISC-V Processor
• Author: Tomislav Katanić
• Mentor: Daniel Hofman (mentor)
• Committee member: Daniel Hofman (predsjednik povjerenstva)
• Committee member: Josip Knezović (član povjerenstva)
• Committee member: Alen Duspara (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2019-07-12, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing

Abstract

Danas tržištem procesora upravljaju tvrtke Intel, AMD, ARM od kojih nema prostora za druge arhitekture procesora. Potpune specifikacije arhitektura AMD, ARM, Intel su zatvorene, te nisu dostupne svima. Kada bi arhitektura sa dobrim skupom instrukcija bila otvorena, dostupna svima, dramatično bi se trebali smanjiti troškovi softvera, dopuštajući mnogo više ponovne upotrebe postojećih otvorenih rješenja. RISC-V ISA nastao je upravo s ovim ciljem, da se napravi dobar skup instrukcija koji će biti otvorena i svima slobodan i besplatan za korištenje. RISC-V arhitektura je još u razvoju te se nadam da će jednog dana biti iznimno korištena. U ovom radu opisan je postupak postavljanja RISC-V Rocket-Chip inačice Linux-a na pločicu ZedBoard, u toj inačici Linux-a se vrši postupak video-kodiranja.

Abstract (english)

Today, the processor market is managed by Intel, AMD, ARM, which do not have room for other processor architectures. Complete specifications of AMD, ARM, Intel architectures are closed and are not available to anyone. If architecture with a good set of instruction was open, accessible to anyone, result of it would be dramatically reduced software costs, allowing much more reuse of existing open solutions. RISC-IS ISA was created with this goal to make a good set of instructions that will be open and free to use. The RISC-V architecture is still in development and I hope that one day it will be widely used. This document describes the procedure for setting the RISC-V Rocket-Chip version of Linux on a ZedBoard. In that version of Linux, the video encoding process is performed.

• Keywords: ZedBoard; arhitektura skupa instrukcija (ISA); RISC-V; Rocket Chip; Linux; video-kodiranje; kvazaar; cross-kompajler
• Keywords (english): ZedBoard; ISA; RISC-V ISA; Rocket Chip; Linux; video encoding; kvazaar; cross-compiler
• Language: croatian
• URN:NBN: urn:nbn:hr:168:620781
• Study programme: Title: Computing; Study programme type: university; Study level: undergraduate; Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2020-01-07 19:02:05