Dizajn gradivnih komponenti procesora arhitekture RISC-V za programabilnu logiku

undergraduate thesis

• Title (english): Design of RISC-V ISA Processor Components for Programmable Logic Implementation
• Author: Filip Horvat
• Mentor: Josip Knezović (mentor)
• Committee member: Josip Knezović (član povjerenstva)
• Committee member: Danko Basch (član povjerenstva)
• Committee member: Igor Čavrak (član povjerenstva)
• Granter: University of Zagreb; Faculty of Electrical Engineering and Computing; Zagreb
• Defense date and country: 2022-07-08, Croatia
• Scientific / art field, discipline and subdiscipline: TECHNICAL SCIENCES; Computing

Abstract

U ovom radu proučava se RISC-V arhitektura skupa instrukcija. Objašnjava se koncept ISA i uspoređuju se njezine 2 glavne vrste, RISC i CISC. Prikazane su značajke RISC-V arhitekture, osnovni skupovi instrukcija te registri. Objašnjeni su formati instrukcija i za svaki navedene instrukcije koje ga koriste. Prikazane su značajke G i C ekstenzija. Proučen je RISC-V i zbirni jezik, formati argumenata instrukcija, relokacijske funkcije, pseudoinstrukcije te pojam makro-op fuzije. Objašnjava se osnovna građa RISC-V procesora i pojam protočne strukture. Pojednostavljeni RISC-V SoC je napravljen u VHDL-u, opisano je kako on i njegova popratna programska potpora za testiranje i ispravljanje grešaka funkcioniraju. Prikazan je PULPissimo, primjer naprednog SoC-a i način kojim se na njemu pokreće program.

Abstract (english)

This thesis studies the RISC-V instruction set architecture. The concept of an ISA is explained and its 2 main types, RISC and CISC are compared. Features of the RISC- V architecture, basic instruction sets and registers are presented. Instruction formats are explained and their respective instructions are listed. Features of G and C extensi- ons are shown. RISC-V assembly language, instruction argument formats, relocation functions, pseudoinstructions and the concept of macro-op fusion are studied. The ba- sic structure od a RISC-V processor and the concept of a pipeline are explained. A simplified RISC-V SoC is made in VHDL, how it and its debugging software function is described. PULPissimo, an example of an advanced SoC and how to run a program on it are shown.

• Keywords: RISC-V; SoC; arhitektura računala; procesor
• Keywords (english): RISC-V; SoC; computer architecture; processor
• Language: croatian
• URN:NBN: urn:nbn:hr:168:321744
• Study programme: Title: Computing; Study programme type: university; Study level: undergraduate; Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Closed access
• Created on: 2023-01-15 10:18:27